Micron Technology Incorporated

Yu Zhang

Dong Pan

Yuan He

Liang Li

Wei Bing Shang

En Peng Gao

Apparatuses and methods for pure-time, self-adopt sampling for RHR refresh. An example apparatus includes a memory bank comprising a plurality of rows each associated with a respective row address, and a sampling timing generator circuit configured to provide a timing signal having a plurality of pulses. Each of the plurality of pulses is configured to initiate sampling of a respective row address associated with a row of the plurality of rows to detect a row hammer attack. The sampling timing generator includes first circuitry configured to provide a first subset of pulses of the plurality of pulses during a first time period and includes second circuitry configured to initiate provision of a second subset of pulses of the plurality of pulses during a second time period after the first time period.

Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling

Embodiments of the disclosure are drawn to apparatuses and methods for analog row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.

Apparatuses and methods for analog row access tracking

A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.

Apparatuses and methods for providing reference voltages

A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval.

Row hammer refresh for content-addressable memory devices

A method of operating a memory device may include receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM). The method may further include storing, during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Moreover, the method may include refreshing each stored RHA of the CAM via a RHR during the RHR interval. Semiconductor devices and an electronic system are also described.

Row hammer refresh for content addressable memory devices

One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarily merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.

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Su Zhou, China

Yu Zhang