Accton Technology Corporation

Yu-Yun Lee

Bang-Jun Tai

Jung-Hui Wei

Chi-Hsu Chen

Yi-Liang Yeh

Yuan-Hsiung Sung

Yi-Da Fan

Kuo-Jui Yu

A network device adapted for sending a synchronization packet to a slave device. The synchronization packet includes a timestamp field and a correction field. The network device includes a counting circuit, a communication chip, and a processor. The counting circuit is configured to provide a calendar time TOD. The communication chip includes a first port, a second port, and a timestamp circuit which has a bit number N. The processor is coupled to the first port of the communication chip. The processor is configured to: obtain a remainder R according to the calendar time TOD and the bit number N; and write the calendar time TOD and the remainder R into the synchronization packet.

Network device

A time synchronization device performs a time synchronization process with a device that provides first and second time values. The time synchronization device includes a packet processing circuit, a time counting circuit, and a processor. The packet processing circuit includes a timestamp counter having an N-bit length, and the packet processing circuit provides first to third time counting values. The processor calculates the first offset value based on the first and second time values and the first and second time counting values; calculates the first adjustment value based on the first offset value and the reciprocal of the frequency of the time counting circuit; calculates a second quotient value and a second remainder value based on the first adjustment value and the N-bit length; and calculates the receiving time of the second synchronization packet based on the N-bit length, the second quotient value, and the third time counting value.

Time synchronization device and time synchronization method

A power sharing device and method thereof are disclosed herein. The power sharing device includes a control unit, multiple regulators and multiple feedback circuits. Each regulator includes a first input terminal, a second input terminal and an output terminal. The control unit generates multiple pulse-width modulation signals. The first input terminal receives one of multiple input voltages. The second input terminal receives one of the pulse width modulation signals. The output terminal selectively outputs an output power. Each feedback circuit is coupled between the second input terminal and the output terminal of one of the regulators. The output terminals of the regulators are coupled to a load, and the regulators selectively output the output power one at a time and in rotation according to the input voltages and duty cycles of the pulse-width modulation signals.

Power sharing device and method thereof

An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval.

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Hsinchu, Taiwan

Yu-Yun Lee