Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Yu Chen

Kuan-Wei Huang

Yi-Nien Su

Yan-Jhi Huang

Jyu-Horng Shieh

Hsin-Yi Tsai

Cheng-Li Fan

Chang-Wen Chen

Chih-Yuan Yao

Yu-Hsin Chan

Hsiang-Lung Tsou

Po-Hsiang Huang

Chi-Hung Liao

Chih-Hao Chen

Jr-Hung Li

Ming-Chung Liang

Ting-Kui Chang

Cai-Ling Wu

Chia-Nan Lin

Jay Chiu

Ching-Yu Chang

Li-Min Chen

Jiing-Feng Yang

Chia-Wei Wu

Meng-Shu Lin

Wei-Hao Lin

In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

Devices with reduced capacitances

A particle removal method includes loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus. The processing chamber is configured to perform a lithography exposure process on a semiconductor wafer. The method also includes fixing the particle attracting member on a reticle holder in the processing chamber in a cleaning cycle, attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer, and loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle. The method also includes loading the semiconductor wafer into the processing chamber, and performing the lithography exposure process on the semiconductor wafer in the processing chamber using a reticle fixed on the reticle holder after the cleaning cycle.

Particle removal method

Embodiments of the present disclosure provide methods for forming conductive lines with dielectric cut features. Particularly, embodiments of present disclosure provide a method for forming conductive line pattern using two patterning processes. A line pattern is formed in the first patterning process. A cut pattern is formed over the line pattern in the second patterning process. The cut pattern is formed by forming cut openings with a width smaller than the line width of the line pattern and then filling the cut opening with a mask material.

Method for reducing line end spacing and semiconductor devices manufactured thereof

A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.

Semiconductor devices and methods of manufacture

A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.

Etching to reduce line wiggling

An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.

Integrated circuit and method for manufacturing the same

A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

Air spacer surrounding conductive features and method forming same

A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.

Semiconductor device and manufacturing method thereof

A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

Self-aligned double patterning

In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.

Lithography method to reduce spacing between interconnect wires in interconnect structure

A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

Semiconductor structure and methods of forming the same

A method includes forming a photoresist layer over a wafer. The photoresist layer is exposed to a pattern of radiation using a photomask. The photoresist layer is developed after the photoresist layer is exposed to the pattern of radiation. The photomask includes a substrate and at least one opaque main feature. The substrate has a recessed region recessed from a first surface of the substrate and has a first width. The at least one opaque main feature protrudes from the first surface of the substrate and has a second width greater than the first width of the recessed region of the substrate. A height of the at least one opaque main feature is greater than a depth of the recess region of the substrate.

Photomask having recessed region

A semiconductor manufacturing system includes a semiconductor processing apparatus. The semiconductor processing apparatus includes a processing chamber configured to perform a semiconductor process on a semiconductor wafer, and a transferring module configured to transfer the semiconductor wafer into and out of the processing chamber. The semiconductor manufacturing system also includes a particle attracting member. The semiconductor manufacturing system also includes a monitoring device configured to control the transferring module to load the particle attracting member into the processing chamber in a cleaning cycle while the semiconductor wafer is not in the processing chamber, and control the transferring module to load the particle attracting member out of the processing chamber after the cleaning cycle. In the cleaning cycle, particles in the processing chamber are attracted to the surface of a coating layer of the particle attracting member due to the potential difference between the coating layer and the particles.

Growing community of inventors

Hsinchu, Taiwan

Yu-Yu Chen