United Microelectronics Corp.

Industrial Technology Research Institute

Nan Ya Technology Corporation

Yu-Ying Lin

Yu-Ren Wang

Chueh-Yang Liu

Neng-Hui Yang

Chun-Wei Yu

I-Cheng Hu

Liang-Ju Chien

Chi-Han Chiou

Shui-Yen Lu

Kuang-Hsiu Chen

Yi-Liang Ye

Ted Ming-Lang Guo

Shao-Hsing Yeh

Yu Shu Lin

Kuan Hsuan Ku

Chun Yao Yang

Zhen Wu

Hsu Ting

Sung-Yuan Tsai

Tai-Yen Lin

Chih-Chien Liu

Chin-Cheng Chien

Chin-Fu Lin

Chun-Yuan Wu

Yu-Shu Lin

Ying-Che Lo

Po-Jen Su

Yen-Hsing Chen

Chun-Jen Chen

Keng-Jen Lin

Tien-I Wu

Hsin-Kuo Hsu

Chung-Yi Hsu

A memory structure and a method of manufacturing the same are provided. The method includes forming a gate structure and a source/drain region in a substrate, in which the source/drain region is next to the gate structure. A dry etching process is performed to form a trench in the source/drain region. A wet etching process is performed to expand the trench to form an expanded trench, in which the expanded trench has a polygonal cross section profile. A bit line contact is formed in the expanded trench.

Memory structure having polygonal shaped bit line contact disposed on a source/drain region

A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

Method of manufacturing memory structure having a hexagonal shaped bit line contact disposed on a source/drain region

Memory structure having a hexagonal shaped bit line contact disposed on a source/drain region

A gas sensing device is adapted to detect a concentration of a target gas. The gas sensing device comprises a dielectric layer, a reference sensing portion, a target sensing portion, and a controller. The dielectric layer is disposed on a surface. The reference sensing portion and the target sensing portion are respectively disposed on a supporting side of the dielectric layer, with said supporting side facing away from the surface. The reference sensing portion includes a first conductive layer and a first sensing layer with low sensitivity to the target gas. The target sensing portion includes a second conductive layer and a second sensing layer with high sensitivity to the target gas. The controller obtains the immittance values of the first conductive layer and the second conductive layer, and calculates a concentration value of the target gas according to the immittance values and a correlation function.

Gas sensing device and gas concentration sensing method

A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

Method for fabricating semiconductor device

An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

Epitaxial process applying light illumination

A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

Semiconductor device and manufacturing method thereof

Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.

Semiconductor device including quantum wires

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

Field-effect transistor

An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

Apparatus for semiconductor wafer treatment and semiconductor wafer treatment

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

Field-effect transistor and method of making the same

A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

Manufacturing method of semiconductor structure for improving quality of epitaxial layers

A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (HO) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.

Method of forming oxide layer

Growing community of inventors

Tainan, Taiwan

Yu-Ying Lin