Advanced Semiconductor Engineering, Inc.

Yu-Ying Lee

Kuang-Hsiung Chen

Sheng-Ming Wang

Tien-Szu Chen

Lu-Ming Lai

Hsiang-Ming Feng

Mei-Yi Wu

Yung-Yi Chang

Yu-Hsuan Tsai

Wun-Jheng Syu

Yu-Tzu Peng

Bing-Yun Cheng

Chih-Cheng Lee

Chun-Che Lee

Li-Chuan Tsai

Mei-Lin Hsieh

A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.

Semiconductor device package

A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.

Package structure, optical structure and method for manufacturing the same

An electronic package structure and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate, a conductive element, and a support structure. The substrate has a bottom surface and a lateral surface angled with the bottom surface. The conductive element is on the lateral surface of the substrate. The support structure is on the bottom surface of the substrate and configured to space the bottom surface from an external carrier. A lateral surface of the support structure is spaced apart from the lateral surface of the substrate by a first distance.

Electronic package structure and method of manufacturing the same

A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.

Semiconductor device package and a method of manufacturing the same

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.

Package structure including an outer lead portion and an inner lead portion and method for manufacturing package structure

A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.

Substrate, semiconductor package thereof and process of making same

A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.

Semiconductor package device having glass transition temperature greater than binding layer temperature

The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

Substrate having a conductive structure within photo-sensitive resin

A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.

Embedded trace substrate structure and semiconductor package structure including the same

A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

Semiconductor device package with a conductive post

In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).

Growing community of inventors

Kaohsiung, Taiwan

Yu-Ying Lee