Xilinx, Inc.

Altera Corporation

Other

Yu Xu

Yohan Usthavia Frans

Kun-Yung Chang

Geoffrey Zhang

Winson Lin

Hongtao Zhang

Zhaoyin D Wu

Alan C Wong

Christopher J Borrelli

Caleb S Leung

Sergey Yuryevich Shumarayev

Cheng-Hsiang Hsieh

Thungoc M Tran

Yang Liu

Ali H Burney

Patrick Satarzadeh

Leon Zheng

Min Wu

Sanjay K Charagulla

Toan Duc Pham

Mengchi Liu

Santiago G Asuncion

Cheng Hsiang Hsieh

Kwong-Wen Wei

Zao Liu

Tianqi Tang

Ku-Yung Chang

An equalizer circuit including a filter, equalization circuitry, and a filter adaptation circuit. The filter is configured to produce a linearized signal based at least in part on a received input signal and a nonlinear transfer function. The equalization circuitry is configured to filter inter-symbol interference (ISI) and detect one or more data symbols in the linearized signal. The equalization circuitry is further configured to produce an error signal indicating an amount of error in the detected data symbols. The filter adaptation circuit is configured to dynamically adjust the nonlinear transfer function of the filter based at least in part on the error signal from the equalization circuitry.

Nonlinear equalizer with nonlinearity compensation

A circuit for determining data error spacing in a data transmitter is disclosed. The circuit comprises a counter; encoding logic configured to receive an output of the counter, wherein the encoding circuit enables generating error spacing information; and a storage element configured to receive an output of the encoding logic.

Circuit for and method of determining error spacing in an input signal

Apparatus and associated methods relate to using a high learning rate to speed up the training of a receiver and switching from a high learning rate to a low learning rate for fine tuning based on exponentially weighted moving average convergence. In an illustrative example, a selection circuit may switch the high learning rate to the low learning rate based on a comparison of a moving average difference eto a predetermined stability criteria Tof the receiver. The moving average difference emay include an exponentially weighted moving average of a difference between two consecutive exponentially weighted moving averages of an operation parameter uof the signal communication channel. By using this method, the training time for the receiver may be advantageously reduced.

Adaptive method to reduce training time of receivers

An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.

Pam multi-level error distribution signature capture

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

Systems and methods for clock and data recovery

A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

Resolving meta-stability in a clock and data recovery circuit

In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.

Signal loss detector

In an example, an apparatus for CDR includes at least one data register, at least one edge register having an input coupled to an output of the at least one data register, and a phase detector having inputs coupled to the output of the at least one data register and an output of the at least one edge register. The apparatus further includes a frequency accumulator coupled to an output of the phase detector, a dynamic gain circuit coupled to the output of the phase detector, and a phase accumulator and code generator circuit configured to generate codes to control a phase interpolator based on an output of the dynamic gain circuit and an output of the frequency accumulator.

Dynamic gain clock data recovery in a receiver

Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.

Clock recovery circuit

Clock data recovery can be accomplished using a phase change determination circuit that generates, based upon detected phase differences between a capture clock signal and data signal, a delta signal and a delta selection signal. A calculation circuit generates a set of phase interpolation (PI) codes from prior and speculative values of the delta signal. A selection circuit selects, in response to the delta selection signal, between the sets of PI codes, which are provided as an output of the clock data recovery device.

Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code or a crossing PI code in a clock and data recovery (CDR) circuit until one or more preset criteria are satisfied. One example method generally includes determining that a condition has been met; based on the determination, stepping, in a CDR circuit, at least one of a data PI code or a crossing PI code for each cycle of a clock; stopping the stepping based on one or more criteria to generate a predetermined state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI code and the crossing PI code; receiving a data stream; and performing clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI code.

Clock data recovery (CDR) phase walk scheme in a phase-interpolater-based transceiver system

A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.

Fast locking CDR for burst mode

A clock data recovery module and a method of operation thereof are described. In an embodiment, a data stream is received. Transitions in the data stream are detected to provide phase signaling for indicating phase relationships to the transitions detected. A lock detector receives the phase signaling. The lock detector accumulates phase information from the phase signaling and temporarily stores an accumulated total of the phase information representative of a code change, and the lock detector determines whether the code change is within a set range over a time period and resets the accumulated total at a conclusion of the time period.

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Palo Alto, CA, United States of America

Yu Xu