China Electronic Technology Corporation, 24th Research Institute

Yu-Xin Wang

Guang-Bing Chen

Dong-Bing Fu

Gang-Yi Hu

Yan Wang

Ting Li

Tao Liu

Jian-An Wang

Ru-Zhang Li

Yong Zhang

Zheng-Bo Huang

Lei Zhang

Can Zhu

Xi Chen

Xu Wang

Jie Pu

Rong-Ke Ye

Yong-Lu Wang

Zheng-Ping Zhang

Yu-Han Gao

Rong-Bin Hu

Jun Yuan

Xing-Fa Huang

Liang Chen

Dai-Guo Xu

Yang Pu

He-Quan Jiang

Yu-Jun Yang

The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Chip ESD protection circuit

A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements. Therefore, by means of the circuit and a method provided in the present invention, adverse influence of the random offset of the comparator on the function and the performance of the parallel-conversion-type analog-to-digital converter is eliminated, thereby greatly improving the speed and the performance of the analog-to-digital converter, in particular the parallel-conversion-type analog-to-digital converter.

Comparator offset voltage self-correction circuit

An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.

Error compensation correction device for pipeline analog-to-digital converter

A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

Sampling device

A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clkgenerate the control signal of the NMOS transistor Pthrough the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

High-speed low-power-consumption dynamic comparator

A dither circuit for high-resolution analog-to-digital converters (ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

Dither circuit for high-resolution analog-to-digital converters

A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.

Successive approximation analog-to-digital converter and conversion method thereof

A layout design method is provided for generating capacitor arrays being described in four steps: first, the wiring mode of unit capacitors is defined allowing the wire being connected to the upper plate to parallel that to the lower one, second, a capacitor array layout is designed with capacitors being distributed in Mh lines, Mh is the maximum of capacitors' lines, the line numbers of Class 1 to Class K capacitors are defined in the unilateral capacitor array, third, the wiring mode is set for capacitor array making sure the lengths of the wires to the upper and lower plates of unit capacitors are equal, at last, parasitic parameters are characterized in ways that verify the layout. A capacitor array is provided as well. By eliminating capacitance mismatching caused by parasitic capacitance, the method works to generate a well-matched capacitor array in an easy and efficient way.

Capacitor array and layout design method thereof

Growing community of inventors

Chongqing, China

Yu-Xin Wang