Faraday Technology Corporation

Yu-Wen Tsai

Jeng-Huang Wu

Cheng-I Huang

Jyh-Herng Wang

Chen-Teng Fan

Chiung-Yu Feng

Peng-Chuan Huang

Chien-Chih Huang

Chien-Chia Huang

A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The fourth device region is arranged between the third device region and the fourth conductor on the substrate.

Layout architecture having high-performance and high-density design

A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Common pass gate layout of a D flip flop

A method for testing power switches using a logic gate tree, the method includes providing a logic gate tree electrically connected to a plurality of power switches, each output node of the plurality of power switches being electrically connected to a corresponding input node of a logic gate of the logic gate tree; applying a pattern of control signals to the plurality of power switches for controlling on-off states of the plurality of power switches; and determining whether an output voltage signal of an output node of the logic gate tree matches a predetermined value corresponding to the pattern of control signals.

Method and apparatus for testing power switches using a logic gate tree

A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.

Method for forming an electric device comprising power switches around a logic circuit and related apparatus

An integrated circuit adapted for ECO and FIB debug comprises: a substrate, a spare cell, a top-layer output terminal pad and a top-layer output terminal pad. The spare cell is disposed in substrate and comprises at least one input terminal and at least one output terminal. The top-layer output terminal pad and the top-layer input terminal pad are disposed in a top metal layer. The top metal layer is disposed over the substrate. The top-layer output terminal pad and the top-layer input terminal pad are electrically coupled to the output terminal and input terminal of the spare cell by a via structure, respectively.

Integrated circuit adapted for ECO and FIB debug

A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid on the floor plan, and the floor plan is divided into a plurality of windows. A plurality of semiconductor cells are placed into a portion of the windows. It is then determined whether a residual area comprising two adjacent windows without functional units and semiconductor cells disposed therein and at least three parallel power lines running theretrough exists. A MOS capacitor is then placed in the detected residual area, serving as a decoupling capacitor.

Placement method for decoupling capacitors

A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew. Alternately, programmable delay buffers can be used for achieving the same goal.

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Hsinchu, Taiwan

Yu-Wen Tsai