Au Optronics Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Wen Lin

Lee-Hsun Chang

Yung-Tse Cheng

Jen-Lang Tung

Yung-Sheng Huang

Shu-Fen Tsai

Chung-Lung Li

Chih-Kuang Kao

Wen-Chi Chien

Huei-Wen Yang

Wei-Cheng Lin

Chih-Yu Peng

Chun-Ching Wei

Jing-Ru Chen

Shu-Wen Cheng

Shih-Ho Chiu

A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Barrier layer for copper interconnect

A gamma correction apparatus comprising a digital to analog converter (DAC), a plurality of compensating circuits, and at least one adjusting circuit is provided. The DAC is used to receive RGB digital signals to further generate analog signals. The analog signals are then transferred to the relative pixel devices through the signal lines on the LCD panel. The compensating circuits inserted between the DAC and the signal lines are used to adjust the analog signals to correct the displaying brightness of the pixel devices. The adjusting circuit connecting to the compensating circuits is used to control the operation of the compensation circuits. In addition, a method for adjusting gamma curves by providing three common voltage levels related to RGB colors individually is also provided to achieve better white balance.

Gamma correction apparatus and a method of the same

A voltage pull-down circuit electrically connected between two scan lines and a bus line includes a transistor and an electrostatic discharge protection device. Each transistor comprises a source, a drain, and a gate electrically connected to one of the scan lines. Each gate is connected to another scan line, the source, and the drain through the electrostatic discharge protection device.

Voltage pull-down circuit

A flat display structure including a substrate, a pixel matrix, a driving circuit and several voltage adapting devices and driving method thereof are provided. Each of voltage adapting devices includes an input terminal, a first control terminal and an output terminal. The input terminal is electrically connected to the i-th gate line Gcorresponding to the i-th pixel row R. The first control terminal is adapted to receive a first control signal. The output terminal is adapted to receive a working voltage.

Flat display structure and method for driving flat display

A control circuit includes a plurality of shift register stages. Each shift register stage is capable of outputting an individual output signal. The output signal is utilized to be a driving signal of next shift register stages. Each shift register stage comprises a transistor for receiving a clear signal CLR. The residual charges of the shift register stage can be released when the clear signal CLR is in a high voltage level. The clear signal CLR is enabled during a non-blanking time of a liquid crystal display (LCD). Each current register stage can use an output signal of another shift register stage which is apart from the current shift register stage by a predetermined interval as the clear signal CLR. The clear signal CLR is used to release the residual charges of the shift register stage before the shift register stage outputs its own output signal.

Control circuit for releasing residual charges

A gate driver includes several first and second circuit units outputting first and second driving signals to odd and even gate lines, respectively, and each of the first circuit units or the second circuit units includes a signal output unit for outputting the driving signal and a shift register unit for outputting a start signal to a next circuit unit. A driving method is also disclosed.

Gate driver and driving method thereof in liquid crystal display

A shift register for use in an LCD is disclosed. The shift register provides better gate driving signals with the lower coupling effect. The shift register includes two switches. The control node of the first switch is electrically coupled to the control node of the second switch. One end of the first switch receives a clock signal, and the other end of the first switch is electrically coupled to one end of the second switch. The other end of the second switch outputs a gate driving signal. Both of the two switches are controlled by a control signal.

Shift register with lower coupling effect and a related LCD

An active device array substrate including a substrate, scan lines, data lines, pixels, a bus line and voltage pull-down circuits is provided. The pixels disposed on intersections of the scan lines and the data lines are arranged in array on the substrate and are electrically connected to the scan lines and the data lines. Each of the voltage pull-down circuits including a transistor and an electrostatic discharge protection device is electrically connected between the scan line and the bus line correspondingly. Each transistor includes a source, a drain, and a gate electrically connected to a next scan line. Each gate is electrically connected to the scan line, the source, the drain and the bus line correspondingly through the electrostatic discharge protection device. The electrostatic discharge protection of the active device array substrate is enhanced effectively by the electrostatic discharge protection device.

Active device array substrate

A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register according to a first clock signal while the signal generating circuit is turned on; a driving circuit, electrically coupled to the signal generating circuit, for generating a driving signal to control the signal generating circuit according to an input signal received from an input end of the shift register; a feedback circuit, electrically coupled to a next stage shift register, for transmitting a control signal while the feedback circuit is turned on by the next stage shift register; and a control switch, electrically coupled to the signal generating circuit and the feedback circuit, for turning off the signal generating circuit while the control switch is turned on by the control signal from the feedback circuit.

Shift register turning off a signal generating circuit according to a signal from a feedback circuit

A system and method for lot priority adjustment. The system includes a database, a calculation unit and an adjustment unit. The database stores at least a committed date for a lot, a throughput rate and a cycle time for respective route operations in a production line, and Work-In-Process (WIP) information of the production line. The calculation unit calculates an x-ratio for the lot on a target route operation according to a current time, the committed date and a remaining cycle time for the lot, calculates a lot weight for the lot according to current loading of a predetermined number of route operations subsequent to the target route operation, and calculates a weighted x-ratio according to the x-ratio and the lot weight. The adjustment unit adjusts a priority for the lot according to the weighted x-ratio.

System and method for lot priority adjustment

An active device array substrate is provided. The active device array substrate includes a plurality of pixel units. Each of the pixel units includes a first active device, a first scan line, a second active device, a second scan line, a data line, a common line, and a pixel electrode. The first scan line is electrically connected to a first gate of the first active device. The second scan line is electrically connected to a second gate of the second active device. The data line is electrically connected to a first source of the first active device. The common line is electrically connected to a second source of the second active device. The pixel electrode is electrically connected to a first drain of the first active device and a second drain of the second active device.

Active device array substrate, liquid crystal display panel, electro-optical device, method for fabricating the same, and methods for driving the same

A shift register includes a plurality of register stages. Each register stage includes an output circuit, a first switching circuit and a second switching circuit. The output circuit is capable of outputting a first driving signal. The first switching circuit is used to pull down the output circuit into a low voltage level when the output circuit is not outputting the first driving signal. The second switching circuit is capable of receiving an input signal. The first switching circuit holds electric charges by the parasitical capacitor resident in the transistor in order to keep the first switching circuit in a turn-on state when the output circuit is not outputting the first driving signal.

Shift register with low stress

A shift register circuit including a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit connected in serial. The second shift register unit includes an output terminal, and a pull down system pulling the voltage of the output terminal of the second shift register unit according to a pull down signal. The fourth shift register unit includes a third switch and a fourth switch. The fourth switch has a control terminal electrically coupled to the second terminal of the third switch and the pull down unit. The fourth shift register unit generates the pull down signal according to the voltage level of the connecting point between the third switch and the fourth switch.

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Hsin-Chu, Taiwan

Yu-Wen Lin