Taiwan Semiconductor Manufacturing Comp. Ltd.

Nan Ya Technology Corporation

Yu-Wei Ting

Kuo-Ching Huang

Chun-Yang Tsai

Chien-Chang Huang

Chin-Ling Huang

Bo Ching Jiang

Tie Jiang Wu

Kuo-Pin Chang

Tie-Jiang Wu

Bo-Ching Jiang

Hung-Ju Li

Wei Ting Hsieh

Chi-Wen Liu

Wen-Ting Chu

Chih-Yang Chang

Tieh-Chiang Wu

Yi Ching Ong

Yi-Hsuan Chen

Kuen-Yi Chen

Yu-Teh Chiang

Tieh Chiang Wu

Chia-Fu Lee

Kuo-Chyuan Tzeng

Chien Hung Liu

Hon-Jarn Lin

Chih-Yang Pai

Tsung-Hao Yeh

Shing-Hwa Renn

Tse-Main Kuo

Chung-Ren Li

Kuo-pin Chang

Ching-En Chen

Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.

Vertical 1T1R structure for embedded memory

A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.

Voltage regulator having variable output capacitance and methods for forming the same

A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

Phase change material switch circuit for enhanced signal isolation and methods of forming the same

One embodiment of the present disclosure provides an optical device which includes a waveguide and a light modulator. The light modulator comprising a bridge segment positioned on the waveguide, wherein the bridge segment comprises a phase-change material. The optical device also includes a heating member. The heating member includes an intermediate segment and two electric contact segments. The intermediate segment is in direct contact with the bridge segment of the light modulator. The two electric contact segments are connected to two ends of the intermediate segment, wherein heat produced from the heating member is directly transferred to the bridge segment of the light modulator thereby inducing a phase transition thereof.

Optical device with phase-change materials and method of fabricating the same

A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes. A first voltage is applied across the first capacitor such that the ferroelectric film is polarized, altering the effective resistance through the device. A second voltage is applied across the first capacitor, such that a leakage current transits the ferroelectric film, and accumulates along an electrode of the second capacitor, and the gate of a transistor, thereby effecting a change to the drain to source resistance of the transistor which may be measured to determine the polarization state of the ferroelectric film.

Ferroelectric tunnel junction memory devices with enhanced read window

Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Phase change material switch with improved thermal confinement and methods for forming the same

A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.

Selector for memory device

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

Heat controlled switch

A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Memory device structure and manufacturing method thereof

An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

Embedded transistor

A device includes a first word line, a resistive random access memory (RRAM) cell, a second word line, and a charge pump circuit. The RRAM cell is coupled to the first word line and is not formed. The charge pump circuit is coupled to the second word line and is configured to provide a negative voltage. Methods of forming the device are also disclosed.

Device and method for forming resistive random access memory cell

Some embodiments of the present disclosure relate to an integrated chip having a vertical transistor device. The integrated chip may have a semiconductor body with a trench extending along first sides of a source region, a channel region over the source region, and a drain region over the channel region. A gate electrode is arranged along a first sidewall of the trench, and a metal contact is arranged on the drain region. An isolation dielectric material is disposed within the trench. The isolation dielectric material is vertically over a top surface of the gate electrode and is laterally adjacent to the gate electrode.

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Taipei, Taiwan

Yu-Wei Ting