Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Coretronic Intelligent Robotics Corporation

Yu-Wei Lee

Sheau-Yung Shyu

Hsiao-Yang Hsu

Cheng-Han Wu

Jyh-Huei Chen

Chih-Hung Wu

Wen-Huei Guo

Ying-Chieh Chen

Chi-Tong Hsieh

I-Ta Yang

Nien-Chao Yang

Lai-Ching Lin

Kuo-Chiang TIng

A photographic device is configured to be assembled on a body of an unmanned vehicle. The photographic device includes a tripod head module, a camera module, a shock-absorbing module, and a detachable supporting plate. The tripod head module includes a first motor disposed along a first axis, a second motor disposed along a second axis, a third motor disposed along a third axis, and a connecting arm. The camera module is pivotally connected to the tripod head module via the connecting arm. The shock-absorbing module includes a frame and a plurality of shock-absorbing balls. The third motor and the shock-absorbing balls are assembled on the frame, and the shock-absorbing balls surround the third motor. The detachable supporting plate is disposed between the frame of the shock-absorbing module and the camera module, and there is a buffer distance between the frame and the detachable supporting plate.

Photographic device and unmanned vehicle

An embodiment is a method including forming a first fin on a substrate, the first fin having a first longitudinal axis, forming a first trench having a first width in the first fin, the first trench dividing the first fin into at least two fin portions, forming a first gate structure and first source/drain regions over one of the at least two fin portions of the first fin, and forming a second gate structure and second source/drain regions over another of the at least two fin portions of the first fin.

Methods of forming FinFETs

A control clocks generator and method thereof for a high speed sense amplifier generates control clocks by utilizing RC delay and gate delay, in combination with reference sensing delay induced from a reference sense amplifier, and thereby, is tracking well for the high speed sense amplifier with process, temperature and voltage variations.

Control clocks generator and method thereof for a high speed sense amplifier

A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB(n) to SB(n), selection switches MB(n) to MB(n), and memory cells M(n) to M(n). The memory cells M(n) to M(n) are electrically coupled to the sub-bit lines SB(n) to SB(n) and the sub-bit line SB(n+1), respectively. When the memory cell M(n) which is connected to SB(n) is read, the sub-bit lines SB(n) to SB(n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB(n) to SB(n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.

Read only memory configuration to reduce capacitance effect between numbers of bit lines

A sense amplifier circuit for sensing data fed to its data input terminal and operating on the data according to a pre-charge signal, a latch signal and a sense amplifier enable signal. The sense amplifier circuit includes a pre-charge sense circuit that receives data from a data input terminal and outputs a first output value as well as a latching circuit that receives the first output value and outputs a second output value within a preset period. The pre-charge sense circuit further includes a first circuit and a second circuit. The first circuit is capable of pre-charging the data input terminal to a preset potential level. The second circuit produces a first output value according to the input data. In addition, the first circuit and the second circuit are connected in parallel between a voltage source and a data input terminal.

Sense amplifier circuit

A double protection virtual ground memory circuit and column decoder. Through the introduction of a double protection circuit, leakage current from the virtual ground memory is reduced and power consumed by the memory circuit is lowered. Ultimately, sensing range of data within the memory by a sense amplifier is improved.

Double protection virtual ground memory circuit and column decoder

An integrated circuit memory comprises an array of non-volatile memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines arranged along the plurality of columns. The array bit lines extend across the array, and include sense lines and ground lines. A plurality of bank bit lines is arranged along the plurality of columns. The bank bit lines extend across corresponding banks in the plurality of banks and are coupled to memory cells in the corresponding banks. A plurality of connection terminals are coupled to the array bit lines. For each array bit line there is at least one connection terminal per bank in the plurality of banks for which the array bit line will be used. A plurality of bank select transistors is provided to act as bank select circuitry. The bank select transistors are operable to selectively connect respective bank bit lines to corresponding connection terminals for array bit lines. The bank select transistors are characterized by allowing independent connection of bank bit lines to sense lines of the plurality of array bit lines, while minimizing the number of transistors in the sensing path. In embodiments described, the bank select transistors allow independent connection of the bank bit lines to both sense lines and ground lines in the plurality of array bit lines.

Growing community of inventors

Hsin-Chu, Taiwan

Yu-Wei Lee