Yangtze Memory Technologies Co., Ltd.

Hubei University

Yu Wang

Ye Tian

Haibo Li

Zhichao Du

Ke Jiang

Xiaojiang Guo

Daesik Song

Jialiang Deng

Zhi Chao Du

Shuang Shuang Li

Qiang Tang

Jin Yong Oh

Chunyuan Hou

Zhuqin Duan

Huangpeng Zhang

Lianjuan Ren

ZhiChao Du

Siyuan Wang

Wenjie Zhang

Lipeng Liu

Hong Guang Song

Khanh Nguyen

Hongbin Zhu

Weihua Cheng

Guanping Wu

Baoyou Chen

Yan Wang

Lixin Ma

Shiyang Yang

Shihui Yang

Xiaodong Mei

Man Lung Mui

Ting Li

Wei Shen

Huamin Cao

Zhuqing Huang

Hai Hui Huang

Xu Hou

Li Yi

Ju Huang

Runxia Li

Yongfu Yang

Danyang Li

Zhefan Li

Shuang Li

Qing Ruan

In certain aspects, a memory device includes a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The plurality of memory cells includes a first set of memory cells configured to be programmed into a first set of programming states each of which is not lower than a first predetermined programming state. The control circuit is configured to perform a first program pass on the first set of memory cells. The control circuit is configured to continue to program at least a first memory cell from the first set of memory cells with one or more first programming voltages. A threshold voltage of the first memory cell is greater than a first verification voltage that corresponds to a first programming state of the first memory cell. The control circuit is configured to perform a second program pass on the first set of memory cells.

Method for programming a memory device to reduce retention error

Examples of the present application provide operation methods of memories, memory devices and systems. In an example, an operation method includes: in response to a first defective memory cell row of a plurality of memory cell rows in the memory being repaired before packaging, invalidating, in a post-package repair mode, a first repair strategy for repairing the first defective memory cell row before packaging, and configuring a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy.

Operation method of memory, memory and memory system

A memory device includes a memory array having memory cells, a page buffer coupled to the memory array through bit lines and including a latch, and a control logic coupled to the page buffer. The control logic is configured to perform a first read operation on the memory cells, and perform a second read operation on the memory cells by dividing the memory cells into a plurality of groups of memory cells, and performing a second read operation on the plurality of groups of memory cells based on a first set of develop times. Each of the first set of develop times is different. The control logic is also configured to perform a third read operation on the memory cells by performing a third read operation on the plurality of groups of memory cells based on a second set of develop times. Each of the second set of develop times is different. The control logic is further configured to determine a read develop time based on the third read operation.

System and method of performing a read operation

A memory device is disclosed. The memory device may include a memory string and a peripheral circuit. The memory string may include a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor. The peripheral circuit may be coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells: after detecting an interrupt signal, perform a clean process that includes turning on at least one of the DSG transistor or the SSG transistor.

Memory device and program operation thereof

A memory device includes a plurality of planes. A method of programming the memory device includes applying a first program pulse to one or more memory cells of a first plane of the plurality of planes, verifying whether each one of the memory cells reaches a predetermined program state, and in response to a preset number of the memory cells in the first plane failing to reach the predetermined program state after the memory cells being verified for a predetermined number of times, bypassing the first plane when applying a second program pulse after the first program pulse.

Method of programming multi-plane memory device

A page buffer includes a first charge/discharge circuit and a second charge/discharge circuit coupled to a bit line. The first charge/discharge circuit is configured to store first bit line forcing information and apply a first bit line forcing voltage to the bit line based on the first bit line forcing information. The second charge/discharge circuit coupled to the bit line and configured to store a second bit line forcing information, and apply a second bit line forcing voltage, different from the first bit line forcing voltage, to the bit line based on the second bit line forcing information. The first bit line forcing voltage and the second bit line forcing voltage are both higher than a programming bit line voltage and lower than a programming-inhabit bit line voltage.

Page buffer, memory device, and method for programming thereof

A memory includes a peripheral circuit and a memory array. The memory array includes word lines. The peripheral circuit includes a driver, a repeater, and a discharge circuit. An output terminal of the driver is coupled with a controlled terminal of the repeater. An output terminal of the repeater is coupled with a controlled terminal of the discharge circuit. The discharge circuit is coupled with a word line in the memory array. The driver is configured to output a first control signal to the repeater. The repeater is configured to output a second control signal to the discharge circuit according to the first control signal.

Memory, drive method, memory system, and electronic device

A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.

Three-dimensional memory device and improved methods of reading the same by shortening read times

The present disclosure provides a memory device, comprising a memory array having memory cells, a page buffer coupled to the memory array through bit lines. The page buffer comprises a latch, and a control logic coupled to the page buffer and configured to: perform a first read operation on the memory cells; select, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state, based on the first read operation; perform a second read operation on the first plurality of memory cells; select, from the first plurality of memory cells, a third plurality of memory cells based on the second read operation; perform a third read operation on the third plurality of memory cells; and determine a read develop time based on the third read operation.

In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. The peripheral circuit is configured to in response to an interrupt during a program operation on a select memory cell of the plurality of memory cells, turn on at least one of the DSG transistor or the SSG transistor. The peripheral circuit is also configured to suspend the program operation after turning on the at least one of the DSG transistor or the SSG transistor.

A memory system includes a memory cell array and a controller coupled to the memory cell array. The controller is configured to control applying a first program voltage to a word line to program memory cells in the memory cell array, the memory cells being coupled to the word line, and in response to receiving a suspend command, control applying a positive bias discharge voltage to the word line when the first program voltage ramps down.

Control method and controller of program suspending and resuming for memory

In a method, a mask is formed on a microstructure over a substrate. The mask includes a first pattern over a first region of the microstructure and a second pattern over a second region of the microstructure. A first etching process is performed to etch the microstructure by providing an etching gas and applying a first bias voltage to the substrate according to the first and second patterns of the mask. A protective layer is subsequently formed by providing a deposition gas and applying a second bias voltage to the substrate to cover the first pattern of the mask. A second etching process is performed to transfer the second pattern of the mask further into the second region of the microstructure. The deposition gas has a higher carbon to fluorine ratio than the etching gas, and the second bias voltage is smaller than the first bias voltage.

Etching process with in-situ formation of protective layer

Read time of three-dimensional memory device

Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions.

Flash memory device with programmable logic circuit

Growing community of inventors

Wuhan, China

Yu Wang