Yangtze Memory Technologies Co., Ltd.

China Three Gorges Corporation

China Three Gorges University

Yu Wang

Weijun Wan

Jialiang Deng

Huichao Dai

Dingguo Jiang

Xiaotao Shi

Junjun Tan

Ke Jiang

ZhiChao Du

Zhenbiao Liu

BiRuo Song

Lei Chen

The present disclosure provides a programming method, a memory device and a memory system. The method includes, based on coupling offsets, dividing target programmed states into N groups, each group corresponding to a different first programmed state, wherein an i-th group has Knumber of different target programmed states and corresponds to an i-th first programmed state. At least two groups of target programmed states have two different numbers of target programmed states. The method also includes performing a first program operation to program memory cells to respective first programmed states; and performing a second program operation to program an i-th group of memory cells at the i-th first programmed state to Knumber of different target programmed states.

Method for programming memory device, memory device and memory system

A water-replenishing fishway with an adaptively-adjusted floating dock is provided. The water-replenishing fishway comprises a fishway body, wherein the bottom of the fishway body is rotationally connected with a floating dock structure, an auxiliary swimming structure is arranged inside the fishway body, and an adjusting structure used to adjust the auxiliary swimming board of the auxiliary swimming structure is arranged on said floating dock structure. The fishway body is excavated with a sliding groove fitting with the sliding block, a first spring is arranged between the sides of the sliding groove and the sliding block, and the bottom of the sliding block is articulated with a roller, which is in contact with the surface of the moving plate of the adjusting structure.

Water-replenishing fishway with adaptively-adjusted floating dock

Disclosed is a memory device comprising: a memory cell array having a plurality of rows of memory cells; a plurality of word lines coupled to the plurality of rows of memory cells respectively; wherein the memory device is configured to perform programming operations on a target memory cell in the plurality of rows of memory cells, wherein during the programming operations: applying a programming voltage to a selected word line corresponding to a row where the target memory cell locates to program the target memory cell to a target programming state; applying a predetermined voltage to the selected word line to reduce voltage changes caused by capacitive coupling between an unselected word line adjacent to the selected word line and the selected word line; and applying a verification voltage to the selected word line to perform verification operations to verify whether a threshold voltage of the target memory cell is larger than a target threshold voltage corresponding to the target programming state based on the predetermined voltage.

Memory device and program operation thereof to reduce capacitive coupling

A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSG), and suspending programming or verifying of the memory cell in a suspend phase.

Memory device and operating method thereof

The disclosure provides a power supply circuit, a memory, a testing device, a memory system and an electronic device, relates to the memory technologies, and may reduce the testing time of the memory and the footprint occupation of the memory. The power supply circuit can include a voltage adjusting circuit and an oscillation circuit. A first voltage output terminal of the voltage adjusting circuit is coupled with a power supply input terminal of a delay chain circuit in the memory and coupled with a power supply input terminal of the oscillation circuit. The voltage adjusting circuit is configured to output a first voltage to the delay chain circuit and the oscillation circuit via the first voltage output terminal. The oscillation circuit is configured to generate a clock signal corresponding to the first voltage. The voltage adjusting circuit is also configured to receive an adjusting signal for adjust the first voltage.

Power supply circuit, memory, testing device, memory system, and electronic device

The present disclosure discloses a buffering fishway suitable for emergent flood discharge with reduction in damage and a buffering method thereof. The buffering fishway includes a fishway body, wherein a migration passage is arranged inside the fishway body, one end of which is rotationally connected with a fixing base, and the other end of which is rotationally connected with a counterweighting floating dock, and a plurality of buffering plates capable of swinging are hinged inside the migration passage, furthermore, the present disclosure also provides a buffering method corresponding to it. The present disclosure effectively reduces the potential energy of the flood and weakens the impact force on the fish. Therefore, the gate dam having this design effectively avoids the fish in the fishway from being fiercely impacted by the flood and easily resulting in damage during discharging flood, having a high protective effect on the fish.

Growing community of inventors

Hubei, China

Yu Wang