Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Tzu Chang

Hung-Jui Kuo

Hui-Jung Tsai

Chia-Wei Wang

A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.

Semiconductor packages and method of forming the same

A method of forming a redistribution structure includes providing a dielectric layer. The dielectric layer is patterned to form a plurality of via openings. A seed layer is formed on the dielectric layer and filling in the plurality of via openings. A patterned conductive layer is formed a on the seed layer, wherein a portion of the seed layer is exposed by the patterned conductive layer. The portion of the seed layer is removed by using an etching solution, thereby forming a plurality of conductive lines and a plurality of vias. During the removing the portion of the seed layer, an etch rate of the patterned conductive layer is less than an etch rate of the seed layer.

Package structure and method of fabrcating the same

Provided is a method for forming a conductive feature including forming a seed layer over a substrate; forming a patterned mask layer on the seed layer, wherein the patterned mask layer has an opening exposing the seed layer; forming a conductive material in the opening; removing the patterned mask layer to expose a portion of the seed layer; and removing the portion of the seed layer by using an etching solution including a protective agent, thereby forming a conductive feature, wherein the protective agent has multiple active sites to adsorb on the conductive material.

Method of fabricating package structure

In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive.

Integrated circuit package and method

A voltage level shifter includes a first switch module having a first transistor and a second transistor, each transistor having a drain, a gate, and a source, wherein the drains of the first and the second transistors are coupled to a first voltage terminal. The voltage level shifter further includes a second switch module coupled between the first switch module and a second voltage terminal, the second switch module including at least six transistors coupled each other, wherein each transistor of the second switch module having a gate for receiving a GATE signal, a GATEb signal, a CORE_INPUT signal, a CORE_INPUTb signal, an IO_INPUT signal, or an IO_INPUTb signal, respectively, wherein the second switch module is designed to produce an output signal at an output node in response to the IO_INPUTb signal and the IO_INPUT signal respectively, irrespective of the CORE_INPUTb signal and the CORE_INPUT signal when the GATE signal is logic low, thereby reducing a leakage current flowing from the first voltage terminal to the second voltage terminal.

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Hsinchu, Taiwan

Yu-Tzu Chang