United Microelectronics Corp.

Yu-Tung Hsiao

Yu-Ren Wang

Yu-Ping Wang

Chen-Ming Huang

Chien-Ming Lai

Kun-Ju Li

Chun-Tsen Lu

Ya-Huei Tsai

Shao-Wei Wang

Keng-Jen Lin

Lu-Sheng Chou

Ching-Hsiang Chiu

Shu-Ming Yeh

Chien-Liang Lin

A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Semiconductor device with metal gate

A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

Semiconductor device having metal gate with nitrogen rich portion and titanium rich portion

A semiconductor process includes the following steps. A dielectric layer is formed on a substrate. A barrier layer is formed on the dielectric layer. An ammonia thermal treatment process with a processing temperature of 650&#xb0; C.&#x2dc;700&#xb0; C. and a nitrogen containing gas annealing process with a processing temperature of 900&#xb0; C.&#x2dc;1000&#xb0; C. are sequentially performed on the barrier layer. The present invention also provides a semiconductor process including the following steps. A dielectric layer is formed on a substrate. A first nitrogen containing thermal treatment process is performed on the dielectric layer. A barrier layer is formed on the dielectric layer. A second nitrogen containing thermal treatment process and then an annealing process are performed in-situ on the barrier layer.

Semiconductor process

The present invention provides a method for forming a stacked layer structure, including: first, a recess is provided, next, an oxide layer is formed in the recess, where the oxide layer has a thickness T, a high-k layer is formed on the oxide layer, a barrier layer is formed on the high-k layer, a silicon layer is then formed on the barrier layer, afterwards, an annealing process is performed on the silicon layer, so as to form an oxygen-containing layer between the silicon layer and the barrier layer, where the oxide layer has a thickness Tafter the annealing process is performed, and satisfies the relationship: (T&#x2212;T)/T&#x2266;0.05, and the silicon layer and the oxygen-containing layer are removed.

Method for forming a stacked layer structure

A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

Semiconductor structure with a multilayer gate oxide and method of fabricating the same

A manufacturing method of a semiconductor structure includes the following steps. A high-k dielectric layer is formed on a semiconductor substrate, and a barrier layer is formed on the high-k dielectric layer. An oxygen annealing treatment is performed after the step of forming the barrier layer; and a capping layer is formed on the barrier layer after the oxygen annealing treatment.

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Tainan, Taiwan

Yu-Tung Hsiao