United Microelectronics Corp.

Yu-Tse Kuo

Chun-Hsien Huang

Shu-Ru Wang

Chun-Yen Tseng

Ching-Cheng Lung

Li-Ping Huang

Chang-Hung Chen

Meng-Ping Chuang

Hsin-Chih Yu

Yi-Ting Wu

Shu-Wei Yeh

Ya-Lan Chiou

Chien-Hung Zordius Chen

Chih-Wei Tsai

Chia-Wei Huang

Yung-Feng Cheng

Tien-Yu Lu

Yi-Wei Chen

Ching-Wen Hung

Shih-Fang Tzou

Chih-Sen Huang

Jen-Yu Wang

Chun-Chieh Chang

Shih-Hao Liang

Yun-San Huang

Chia-Chun Sun

Yu-Fang Chen

Koji Nii

Chien-Hung Chen

Ssu-I Fu

Chih-Kai Hsu

Yu-Hsiang Hung

Jyh-Shyang Jenq

Cheng-Tung Huang

Yuichiro Ishii

Jia-Rong Wu

Tong-Yu Chen

Hung-Chan Lin

Shao-Hui Wu

Tsung-Hsun Wu

Po-Chun Yang

Yung-Ching Hsieh

Jian-Jhong Chen

Wei-Chi Lee

Chung-Cheng Tsai

Bo-Chang Li

Chih-Ming Su

Han-Tsun Wang

Jhen-Siang Wu

Tzu-Feng Chang

Tsan-Tang Chen

Yen-Hsueh Huang

Chang-Ting Lo

Ting-Hao Chang

Shou-Sian Chen

Ting-Chia Chang

Jheng-Tai Yan

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Layout pattern of magnetoresistive random access memory

The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

Spin-orbit torque magnetic random access memory circuit and layout thereof

The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Layout pattern of static random access memory and the forming method thereof

The present invention provides a layout pattern of static random access memory, comprising a PU(first pull-up transistor), a PU(second pull-up transistor), a PDA (first pull-down transistor), a PDB (second pull-down transistor), a PDA (third pull-down transistor), a PDB (fourth pull-down transistor), a PGA (first access transistor), a PGB (second access transistor), a PGA (third access transistor) and a PGB (fourth access transistor) located on the substrate. The PDA and the PDB are connected in parallel with each other, the PDA and the PDB are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Layout pattern of static random access memory

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Layout of semiconductor memory device

The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Semiconductor layout pattern and forming method thereof

A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

Ternary content addressable memory and two-port static random access memory

A layout pattern of a two-port ternary content addressable memory (TCAM) includes a first storage unit, a second storage unit, a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit are positioned in a first side area of a side and a second side area of another side of the layout pattern, respectively. The first storage unit and the second storage unit are positioned in a first middle area and a second middle area between the first side area and the second side area, respectively. The first storage unit is connected to the first comparison circuit through a first gate structure and connected to the second comparison circuit through a second gate structure. The second storage unit is connected to the first comparison circuit through a third gate structure and connected to the second comparison circuit through a fourth gate structure.

Layout pattern of two-port ternary content addressable memory

A memory includes (n&#x2212;1) non-volatile cells, (n&#x2212;1) bit lines and a current driving circuit. Each of the (n&#x2212;1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n&#x2212;1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n&#x2212;1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n&#x2212;1) non-volatile cells.

Memory including non-volatile cells and current driving circuit

A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.

Two-port ternary content addressable memory and layout pattern thereof, and associated memory device

A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.

Ternary content addressable memory unit capable of reducing charge sharing effect

A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL) and a gate of a first pull-down device (PD). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL) and a gate of a second pull-down device (PD) and the gate of the PDis directly under the gate of the PD

Layout pattern of a static random access memory

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Tainan, Taiwan

Yu-Tse Kuo