Anaglobe Technology, Inc.

Yu-Tsang Hsieh

Yao-Wen Chang

Po-Hung Lin

Yu-Sheng Lu

Chun-Yu Lin

Chih-Che Lin

I-Peng Wu

Sheng-Jung Yu

Hung-Chih Ou

Min-Hsuan Chung

Yan-Lin Chen

Vincent Weihao Hsiao

Kuan-Cheng Chen

Hung-Yun Hsu

Nai-Chen Chen

Yang Hsu

A method for generating analog schematic diagram based on building block classification and reinforcement learning is disclosed. First of all, deeper relationship features among devices with building block classification are obtained. Secondly, the device leveling gives an initial device placement topology resulting from the current/signal flows in the circuit netlist. Thirdly, reinforcement learning is applied to refine placement and routing topologies by embedding the building blocks and current/signal flow information into feature vectors. Pattern routing and maze routing algorithms are performed for local and global interconnections, respectively, followed by placement adjustment for density balancing and space minimization to obtain aesthetic analog circuit schematics.

Method for generating analog schematic diagram based on building block classification and reinforcement learning

A method of warpage-aware floorplanning for heterogeneous integration structure is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a performing a layout partitioning to divide a layout into a plurality of grids; performing an initial floorplanning by assigning first geometric relations between a plurality of dies such that an effective material of each grid of the plurality of grids is determined; performing a global floorplanning to change the first geometric relations between the plurality of dies to second geometric relations to optimize warpage effect of the heterogeneous integration structure; and performing a detailed floorplanning to determine die order of placement based on material differences between the plurality of dies and an interposer.

Method of warpage-aware floorplanning for heterogeneous integration structure

A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Method for parallelism-aware wavelength-routed optical networks-on-chip design

A method of WDM-aware optical routing for on-chip devices is proposed, which is executed by a computer, the method comprising using the computer to perform the following steps of: performing a path separation to identify signal net candidates; performing a path clustering to find path clusters of the signal net candidates; performing an endpoint placement to find legal locations for WDM endpoints; and performing a pin-to-waveguide routing all nets to corresponding WDM waveguides.

Method of wavelength-division-multiplexing-aware clustering for on-chip optical routing

A method for parasitic-aware capacitor sizing and layout generation is proposed, which is executed by a computer, the method comprising using the computer to perform the following: creating a capacitor sizing and parasitic matching sequence to represent a unit capacitor size, routing topology and routing patterns of a plural of nets in a capacitor network. Next, a shielding assignment is performed to create a number of shielding portions of each net in the plural of nets. Then, a fitness evaluation of configurations of the capacitor sizing and parasitic matching sequence is performed. A shielding net routing is performed to compensate unmatched parasitic capacitance of the configurations of the capacitor sizing and parasitic matching sequence.

Method for parasitic-aware capacitor sizing and layout generation

A method for analog circuit placement is proposed. The method comprises inputting a plurality of modules, a netlist and a constraint file. Next, it is performing a step of establishing a QB-tree construction. Then, a node perturbation of QB-tree is performed after establishing the QB-tree construction. Subsequently, it is performing a step of a look-ahead constraint checking to check whether meet constraints of the constraint file or not, followed by performing a QB-tree packing when meet constraints of the constraint file. Next, it is performing a process of performing a cost evaluation.

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Hsinchu County, Taiwan

Yu-Tsang Hsieh