Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Ting Tsai

Chung-Liang Cheng

Chyi-Tsong Ni

Hong-Ming Lo

Chun-Chih Lin

Chia-Ta Hsieh

Su-Yu Yeh

Yu-Cheng Shen

Hung-Chih Wang

Chi-Wei Ho

Wen-Cheng Cheng

Tsung-Hua Yang

Che-Hung Liu

Kao-Chao Lin

Ching-Jing Wu

Ching-Tzer Weng

Shao-Shuo Wu

A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Fluorine-free interface for semiconductor device performance gain

A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.

System and method for cleaning a pre-clean process chamber

An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.

Apparatus and method of manufacturing interconnect structures

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

Semiconductor device and method of manufacturing the same

A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.

Semiconductor arrangement and method of making

A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium layer on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Growing community of inventors

Taipei, Taiwan

Yu-Ting Tsai