Taiwan Semiconductor Manufacturing Comp. Ltd.

Nan Ya Technology Corporation

Industrial Technology Research Institute

Au Optronics Corporation

Chunghwa Picture Tubes, Ltd.

Wintek Corporation

National Cheng-kung University

Young Lighting Technology Corporation

Juluen Enterprise Co., Ltd.

Champ Vision Display Inc.

Tpk Holding Co., Ltd.

Du Pont Apollo Limited

Parabellum Strategic Oppurtunities Fund LLC

Yu-Ting Lin

Chun-Chieh Wang

Yu-Sheng Wang

Yueh-Ching Pai

Yinlung Lu

Jun He

Yung-Liang Kuo

Shih-Chieh Chang

Cheng-Wei Chang

Min-Hsiu Hung

Mao-Ying Wang

Huai-Tei Yang

Chiang-Lin Shih

Ching-Hwanq Su

Huang-Yi Huang

Sheng-Wen Chen

Wei-Hsun Lin

Lai-Cheng Tien

Wei-hsun Lin

Ming-Hsing Tsai

Chi-Cheng Hung

Ting-Chun Wang

Yian-Liang Kuo

Ken-Yu Chang

Lin-June Wu

Wei-Ming You

Hung-Yi Huang

Ya-Hui Tsai

Ming-Kung Wu

Liang-Yueh Ou Yang

Yi-Hsiang Chao

Chun Chieh Wang

Uway Tseng

Kao-Feng Lin

Hsueh-Han Lu

Tien-Pei Chou

Ying-Lang Wang

Yun-Yue Lin

Chin-Ku Liu

Kuo-Chang Su

Yu-Chang Lin

Sheng-Hsuan Lin

Che-Hao Chang

Yu-Ku Lin

Lun-Kuang Tan

Tung-Chuan Wu

Liang-Chen Lin

Jhong-Hao Wu

Jun-Nan Nian

Yung-Sheng Huang

Li-Yen Fang

Keng-Hao Chang

Wei-Chuan Fang

Kuo-Tang Huang

Ta-Chih Peng

Chia Ping Lo

Ko-Yi Lee

Chien-Yi Chen

Wei-Yao Chiu

Chun-Lung Chang

Yan-Hua Lin

Chia-Chi Chen

Huai-Chung Hsu

Wei-Yu Chen

Shiu-Ko JangJian

Cheng-Ta Wu

Chen-Yuan Kao

Wei-Ming Huang

Ping-Wen Huang

Yaw-Ming Tsai

Rueijer Lin

Yi-Ying Liu

Maw-Song Chen

Hung-Chun Li

Ching-Hsiang Cheng

Hung-Chang Hsu

Ming-Hui Lin

Pei-Jhen Wu

Tsang-Po Yang

Chun-Wen Nieh

Min-Feng Ku

Chih-Cherng Jeng

Wei-Chih Hsu

Yu-Wen Cheng

Chuan-Sheng Wei

Kuo-Feng Hung

I-Li Chen

Wen-Jun Zeng

Po-Kai Hsiao

Yi-Ting Huang

Po-Kang Ho

Chin-Kuei Chang

Hsiao-Ping Liu

Hong-Ming Wu

Wei-Min Chen

Chao-Ching Liu

Hsiang-Wei Yin

Hung-Chun Tsai

Chia-Chun Fang

Shang-Ting Huang

The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

Method of manufacturing semiconductor structure using multi-layer hard mask

A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a sacrificial structure disposed on a substrate; arranging a photomask to cover the sacrificial structure, wherein the photomask includes a plurality of transparent portions, a plurality of central opaque portions, at least one first edge opaque portion and at least one second edge opaque portion between the first edge opaque portion and the central opaque portions; removing portions of the sacrificial structure to form a plurality of central openings, at least one first edge opening and at least one second edge opening through the central opaque portions, the first edge opaque portion, the second edge opaque portion and the transparent portions; and forming at least one edge word line on the substrate through the second edge opening and forming a plurality of central word lines on the substrate through the central openings.

Method of manufacturing semiconductor structure comprising edge word line and central word line

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a source/drain (S/D) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the S/D epitaxial layer. The semiconductor structure includes a contact plug barrier formed over the S/D epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.

Semiconductor structure with source/drain multi-layer structure and method for forming the same

A flexible warning light includes a lamp housing including a base with a bottom plate, a flexible lamp shell covering base and an accommodation space defined between base and flexible lamp shell, and a light-emitting device mounted in the accommodation space and having at least one light-emitting element on the top of a flexible circuit board of a light-emitting device on the top, and a first heat sink and multiple second heat sinks on the bottom. The flexible lamp shell will elastically deform in accordance with the surface curvature of a preset vehicle body to drive first heat sink and second heat sinks to deform so that the base can be closely attached to the curved surface of the preset vehicle body through the deformation of the first heat sink and the second heat sinks, so as to achieve the effect of being more compliant with the curved vehicle body.

Flexible warning light

The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.

Method and device for wafer-level testing

Semiconductor structure and method of manufacturing the same including buried word lines of different widths

A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.

Low resistant contact method and structure

The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.

Method and system for wafer-level testing

A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Repackaging IC chip for fault identification

A semiconductor device is provided. The semiconductor device includes a substrate defining a plurality of trenches; and a plurality of bit line contacts disposed on the substrate, wherein at least one of the plurality of bit line contacts is disposed within one of the trenches defined by the substrate, wherein the plurality of trenches has a first row and a second row, and a pitch of the first row is different from a pitch of the second row.

Semiconductor device with bit line contacts of different pitches

A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Semiconductor structure

An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Forming trench in IC chip through multiple trench formation and deposition processes

A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Test structure for use in dynamic random access memory and manufacturing method thereof

The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

Contact metallization process

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Conductive feature formation and structure

Growing community of inventors

Tainan, Taiwan

Yu-Ting Lin