United Microelectronics Corp.

Other

Yu-Ting Hung

En-Chiuan Liou

Chia-Hsun Tseng

Shin-Feng Su

Yu-Te Chen

Meng-Lin Tsai

Feng-Yi Chang

Chun-Lung Chen

Kun-Yuan Liao

Chia-Lin Lu

Wei-Hao Huang

Che-Yi Lin

Cheng-Yao Chen

Yi-Wen Cheng

Wen-Ting Chen

Chiung-Lin Hsu

Tsu-Ying Wu

Shang-Nan Chou

Jan-Fu Yang

Provided herein relates to DNA polymerase variants and kits including the same, where the DNA polymerase variant has an improved function and activity of performing template-independent nucleic acids synthesis using canonical nucleotides and non-canonical nucleotide analogues in a thermotolerant manner.

Polymerase variants for template-independent enzymatic nucleic acids synthesis and kit comprising the same

A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.

Method of forming non-continuous line pattern and non-continuous line pattern structure

A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly.

Method of fabricating semiconductor structure with improved critical dimension control

A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.

Method of adjusting channel widths of semiconductive devices

A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.

Method of fabricating a semiconductor structure with a self-aligned contact

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Hsinchu, Taiwan

Yu-Ting Hung