Nxp Usa, Inc.

Freescale Semiconductor,inc.

Yu-Ting David Wu

Joseph Gerard Schultz

Nick Yang

Enver Krvavac

Jeffrey Kevin Jones

Elie A Maalouf

Ramanujam Srinidhi Embar

Damon G Holmes

Abdulrhman M S Ahmed

Mario M Bokatius

Hussain Hasanali Ladhani

Shishir Ramasare Shukla

Ibrahim Khalil

Humayun Kabir

Ricardo Uscola

Lu Wang

James Krehbiel

Daniel Joseph Lamey

Weng Chuen Edmund Neo

A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.

Transistor circuits with shielded reference transistors

A Doherty amplifier includes a peaking amplifier, a carrier amplifier, and a combining node electrically connected to the carrier amplifier and the peaking amplifier. The Doherty amplifier includes a harmonic control circuit coupled to the combining node. The harmonic control circuit includes an inductor and a capacitor and the inductor and capacitor are connected in series between the first current conducting terminal and a ground reference node. An inductance value of the inductor of the harmonic control circuit and a capacitance value of the capacitor of the harmonic control circuit are selected to terminate second order harmonic components of a fundamental frequency of a signal generated by the carrier amplifier.

Doherty amplifiers and amplifier modules with shunt inductor and capacitor circuit for improved carrier harmonic loading

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

Power amplifier with a power transistor and an electrostatic discharge protection circuit on separate substrates

An embodiment of a Doherty amplifier includes a module substrate, first and second surface-mount devices coupled to a top surface of the module substrate, and an impedance inverter line assembly. The first and second surface-mount devices include first and second amplifier dies, respectively. The impedance inverter line assembly is electrically connected between outputs of the first and second amplifier dies. The impedance inverter line assembly includes an impedance inverter line coupled to the module substrate, a first lead of the first surface-mount device coupled between the first amplifier die output and a proximal end of the impedance inverter line, and a second lead of the second surface-mount device coupled between the second amplifier die output and a distal end of the impedance inverter line. According to a further embodiment, the impedance inverter line assembly has a 90 degree electrical length at a fundamental operational frequency of the Doherty amplifier.

Doherty amplifier with surface-mount packaged carrier and peaking amplifiers

An amplifier includes a driver stage amplifier transistor and a final stage amplifier transistor, which are integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance. The final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.

Multiple-stage power amplifiers and devices with low-voltage driver stages

An embodiment of a module (e.g., an amplifier module) includes a substrate, a transmission line, and a ground plane height variation structure. The substrate is formed from a plurality of dielectric material layers, and has a mounting surface and a second surface opposite the mounting surface. A plurality of non-overlapping zones is defined at the mounting surface. The transmission line is coupled to the substrate and is located within a first zone of the plurality of non-overlapping zones. The ground plane height variation structure extends from the second surface into the substrate within the first zone. The ground plane height variation structure underlies the transmission line, a portion of the substrate is present between the upper boundary and the transmission line, and the ground plane height variation structure includes a conductive path between an upper boundary of the ground plane height variation structure and the second surface.

Amplifiers and amplifier modules with ground plane height variation structures

Embodiments of a multiple-path amplifier (e.g., a Doherty amplifier) and a module housing the amplifier include a first amplifier (or first power transistor die) with a first output terminal, a second amplifier (or second power transistor die) with a second output terminal, and an impedance inverter line assembly electrically connected between the first and second output terminals. The impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals. In various embodiments, the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network.

Multiple-path amplifier with series component along inverter between amplifier outputs

Systems for providing isolation of a bias signal relative to a radio frequency (RF) signal in an integrated circuit, and related circuits, modules, and methods, are disclosed herein. In one example embodiment, a system includes an inductor, a bypass capacitor, and a transmission line segment, which includes first and second ends and extends between the first and second ends. The first end is at least indirectly coupled to the bypass capacitor, the second end is at least indirectly coupled to a first additional end of the inductor, and a second additional end of the inductor is configured to be coupled at least indirectly to a device through which the RF signal is being communicated. The transmission line segment is configured to impart a non-negligible phase shift to a signal communicated between the first and second ends, or is configured to have a non-negligible effective inductance.

System and method for providing isolation of bias signal from RF signal in integrated circuit

An amplifier module is provided. The amplifier module includes a multi-layer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multi-layer PCB. A second power transistor die is mounted at the top surface of the multi-layer PCB. An impedance inversion element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combining node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled at the combining node.

Amplifiers and amplifier modules having stub circuits

A Doherty amplifier module includes first and second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. A phase shift and impedance inversion element is coupled between the outputs of the first and second amplifier die. A shunt circuit is coupled to the output of either or both of the first and/or second amplifier die. The shunt circuit includes a series coupled inductance and high-Q capacitor (e.g., a metal-insulator-metal (MIM) capacitor), and the shunt circuit is configured to at least partially resonate out the output capacitance of the amplifier die to which it is connected.

Amplifiers and amplifier modules with shunt inductance circuits that include high-Q capacitors

An embodiment of a Doherty amplifier module includes a substrate, a first amplifier die, and a second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. The first and second amplifier die each also include an elongated output pad that is configured to enable a pluralities of wirebonds to be connected in parallel along the length of the elongated output pad so that the pluralities of wirebonds extend in perpendicular directions to the first and second signal paths.

Amplifier die with elongated side pads, and amplifier modules that incorporate such amplifier die

A Doherty amplifier module includes first and second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. A phase shift and impedance inversion element is coupled between the outputs of the first and second amplifier die. A shunt inductance circuit is coupled to the output of either or both of the first and/or second amplifier die. Each shunt inductance circuit at least partially resonates out the output capacitance of the amplifier die to which it is connected to enable the electrical length of the phase shift and impedance inversion element to be increased.

Doherty amplifiers and amplifier modules with shunt inductance circuits that affect transmission line length between carrier and peaking amplifier outputs

A radio frequency (RF) chip capacitor circuit and structure are provided. The circuit and structure include a plurality of capacitors connected in series. Each capacitor of the plurality includes a first plate formed from a first metal layer and a second plate formed from a second metal layer. A first two adjacent capacitors of the plurality include first plates formed in a first contiguous portion of the first metal layer or second plates formed in a second contiguous portion of the second metal layer. Each capacitor of the plurality may include a dielectric layer disposed between the first plate and the second plate.

Chip capacitor circuit and structure therefor

A multiple-stage amplifier includes a driver stage die and a final stage die. The final stage die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a first transistor. The driver stage die includes another type of semiconductor substrate (e.g., a silicon substrate), a second transistor, and one or more secondary circuits that are electrically coupled to a control terminal of the first transistor. A connection (e.g., a wirebond array or other DC-coupled connection) is electrically coupled between an RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die. The secondary circuit(s) of the driver stage die include a final stage bias circuit and/or a final stage harmonic control circuit, which are electrically connected to the final stage die through various connections.

Growing community of inventors

Schaumburg, IL, United States of America

Yu-Ting David Wu