Chipmos Technologies Inc.

Chipmos Technologies (bermuda) Ltd

Chipmos Technology Inc.

Yu-Tang Pan

Shih-Wen Chou

Cheng-Ting Wu

Hui-Ping Liu

Men-Shew Liu

Geng-Shin Shen

Chun-Hung Lin

Chun-Ying Lin

A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

Manufacturing method of chip package structure

A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.

Chip package structure and manufacturing method thereof

A chip package structure including a leadframe, a chip, bonding wires and an encapsulant is provided. The leadframe includes a die pad, leads and an insulating layer. The die pad includes a chip mounting portion and a periphery portion. At the periphery portion, the die pad has a second upper surface lying between a first upper surface and a lower surface of the die pad. Each lead includes a suspending portion and a terminal portion. The suspending portion connects to the terminal portion and extends from the terminal portion towards the die pad. The insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad. The chip is disposed on the chip mounting portion. The bonding wires electrically connect the chip to the suspending portions. The encapsulant covers the chip, the bonding wires, the insulating layer, and the leadframe.

A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.

Semiconductor package structure and manufacturing method thereof

The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires. Whereby, the package of the invention can have more inputs/outputs terminals, and the insulating layer can prevent moisture permeation from corroding the joints between the wires and the first pads and the second ends of the traces, thus increasing the reliability of the package of the invention.

Quad flat no lead (QFN) package

A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Chip package without core and stacked chip package structure

A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate.

Chip-stacked package structure and method for manufacturing the same

A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

Chip-stacked package structure

A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.

Chip package structure

A chip package including a metal layer, a film-like circuit layer, a chip, a lead matrix and an encapsulant is provided. The film-like circuit layer disposed on the metal layer includes an insulating film disposed on the metal layer and a circuit layer disposed on the insulating film. The circuit layer has a plurality of conductive traces. The chip disposed above the metal layer is electrically connected to the conductive traces. The lead matrix having a plurality of leads is disposed outside the chip. At least part of the leads are electrically connected to the conductive traces. The encapsulant at least encapsulates the chip, the film-like circuit layer, at least part of the leads, and at least part of the metal layer.

Chip package and method of manufacturing the same

A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance layer is formed on the patterned circuit layer and then patterned to expose parts of the patterned circuit layer. After a second film is formed on the solder resistance layer and the first film is removed, a chip is disposed on the first surface and electrically connected to the patterned circuit layer. A molding compound is formed to cover the patterned circuit layer and fix the chip onto the patterned circuit layer. After that, the second film is removed.

Manufacturing process for chip package without core

A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.

A method for manufacturing a light emitting chip package includes bonding a patterned metal plate having at least a thermal enhanced plate and many contacts around the same to a substrate and bonding a film-like circuit layer to the patterned metal plate. Many conductive wires are formed to connect the film-like circuit layer and the contacts. Thereafter, at least a first molding is formed on the substrate to encapsulate the patterned metal plate, the conductive wires and a portion of the film-like circuit layer. At least one light emitting chip disposed on the film-like circuit layer exposed by the first molding has many bumps to which the light emitting chip and the film-like circuit layer are electrically connected. A cutting process is performed to form at least one light emitting chip package, and the substrate is removed. Therefore, heat dissipation efficiency of the light emitting chip package can be improved.

Light emitting chip package and manufacturing method thereof

A light emitting chip package having a carrier, at least one light emitting chip and a thermal enhanced cover is provided. The carrier includes a plurality of through holes. The light emitting chip is disposed on the carrier. The light emitting chip has an active surface, a back surface opposite to the active surface and a plurality of bumps disposed on the active surface. The light emitting chip is electrically connected to the carrier through the bumps. The thermal enhanced cover is disposed on the carrier to expose at least one side of the light emitting chip. The thermal enhanced cover includes a cover body and a plurality of protrusions connected thereto. A portion of the cover body is above the back surface of the light emitting chip. The protrusions are respectively inserted through the through holes. Therefore, the thermal dissipation efficiency of the light emitting chip package is improved.

Growing community of inventors

Tainan County, Taiwan

Yu-Tang Pan