Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Tai Chia

Chung-Shi Chiang

Tse-Lun Tsai

Tzu-Jin Yeh

Hsin-Yi Lee

Harry Chuang

Chien-Wen Chen

Ke-Wei Su

Hsien-Chang Wu

Chung-Kai Lin

Jaw-Kang Her

Ming-Ta Yang

Shiun-Huan Lai

Victor C Y Chang

Chung-Lun Kuo

Jc Guo

A computer-based system and method for generating a primary document characterizing a device from multiple secondary documents is provided. In one example, the method includes defining a primary document template and multiple input files. Each input file defines the source and type of information for a section of the primary document template. A document generation engine parses the secondary documents and inserts information from them into the primary document template based on the input files. After the primary document is generated, related technologies or devices may be identified and notified of changes to the device in the primary document. The related technologies or devices may then be updated if desired.

System and method for compiling documents and tracking technology changes in a semiconductor manufacturing environment using a document generation engine

Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.

Process related deviation corrected parasitic capacitance modeling method

An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.

Inductor Q value improvement

A capacitor has at least two layers of substantially parallel interdigitated strips. The strips of each layer are alternately connected to a first and a second bus. The first and second buses of each layer are interconnected to first and second buses of an adjacent layer. The strips of each layer are approximately perpendicular to strips of an adjacent layer. The capacitor further includes dielectric material between strips of the same and different layers. A method of fabricating the capacitor includes forming at least two layers of substantially parallel interdigitated strips which are alternately connected to first and second buses of each layer. The buses of each layer are connected to the respective buses of an adjacent layer. The strips of one layer are approximately perpendicular to the strips of an adjacent layer. Dielectric material is formed between strips of the same and different layers.

Interdigitated capacitor structure for an integrated circuit

A method of characterizing gate leakage current in the fabrication of integrated circuits is described. A MOSFET model is provided including a gate electrode deposed over a gate oxide layer on a substrate and source and drain regions associated with the gate electrode. Device current is measured at four terminals simultaneously wherein one of the terminals is a drain terminal. The other terminals are the source, gate, and substrate. The portion of the device current measured at the drain terminal that is contributed by gate current is evaluated. The evaluated gate current contribution is subtracted from the drain terminal current measurement to obtain pure drain current. Fitting procedures are performed to obtain curves for the device currents. The pure drain current is used to extract mobility model parameters.

Characterization methodology for the thin gate oxide device

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San Jose, CA, United States of America

Yu-Tai Chia