United Microelectronics Corp.

Yu-Shiang Yang

Te-Hung Wu

Chun-Hsien Huang

Ming-Jui Chen

Hui-Fang Kuo

Yung-Feng Cheng

Cheng-Te Wang

Chuen Huei Yang

Shih-Ming Kuo

Hsiang-Yun Huang

Lun-Hung Chen

A method of forming a pattern is disclosed. At first, a layout pattern is provided to a computer system. The layout pattern includes at least a first strip pattern and at least a second strip pattern, and a width of the second strip pattern is substantially larger than a width of the first strip pattern. Subsequently, the second strip pattern neighboring the first strip pattern is defined as a selected pattern. Then, an assist pattern is formed in the selected pattern, and the assist pattern does not overlap a center line of the selected pattern. The layout pattern and the assist pattern are further outputted through the computer system onto a mask.

Mask and method of forming pattern by using the same

A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns.

Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device

A mask includes a substrate, at least a first strip pattern, at least a second strip pattern and an assist pattern. A width of the second strip pattern is substantially larger than a width of the first strip pattern. The assist pattern is disposed in the second strip pattern neighboring the first strip pattern, and the assist pattern does not overlap a center line of the second strip pattern.

A method optical proximity correction includes the following steps. First, a layout of an integrated circuit with an exposure intensity specification is provided. The integrated circuit includes a plurality of patterns and each pattern has an exposure intensity distribution. Second, a quadratic polynomial equation of each exposure intensity distribution is approximated. Third, a local extreme intensity of each exposure intensity distribution is computed by fitting the quadratic polynomial equation. Fourth, the local extreme intensity is determined whether violating the exposure intensity specification or not. Then, the layout is corrected when the local extreme intensity violates the exposure intensity specification.

Method and computer-readable medium of optical proximity correction

A method to compensate optical proximity correction adapted for a photolithography process includes providing an integrated circuit (IC) layout. The IC layout includes active regions, a shallow trench isolation (STI) region and ion implant regions overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region disposed in the STI region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Then, the corrected IC layout is transferred to a photomask.

Method to compensate optical proximity correction

A method to compensate optical proximity correction adapted for a photolithography process is provided. An integrated circuit (IC) layout firstly is provided. The IC layout includes active regions and a shallow trench isolation (STI) region. The STI region is a region except the active regions. The IC layout further includes ion implant regions which are overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Each photoresist line width compensation region is disposed in the STI region. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Finally, the corrected IC layout is transferred to a photomask.

A method for correcting layout pattern is disclosed. The method includes the steps of: providing a layout pattern having at least one segment; forming a rule-checking rectangle from the segment, wherein the rule-checking rectangle comprises at least one square; verifying whether the square of the rule-checking rectangle overlaps other layout pattern; removing the portion of other layout pattern overlapped by the square to obtain a corrected layout pattern; and outputting the corrected layout pattern to a mask.

Method for correcting layout pattern using rule checking rectangle

A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.

Method for selectively amending layout patterns

A mask pattern correction method is provided. The method comprises the following steps. An original layout, which has a plurality of device patterns, is provided. Then, a simulation process is performed on the device patterns to correspondingly form a plurality of simulated patterns. Thereafter, the simulated patterns are analyzed to select a plurality of unsaturated patterns from the simulated patterns. Finally, the device patterns in the original layout corresponding to the unsaturated patterns respectively are rotated.

Mask pattern correction and layout method

The present invention provides a method of checking and correcting a mask pattern. The method includes inputting a mask pattern, wherein the mask pattern includes at least a segment; inputting a process rule; selecting an edge, which fits in with an orientation model, as a target edge, wherein two ends of the target edge are an ahead direction and a behind direction, and the ahead direction and the behind direction each further comprise at least a checking point; identifying an interacting edge from the mask pattern along the checking directions; performing a process rule check to provide a correcting value; performing a first correction to provide a first bias to the target edge; and performing a second correction to provide a second bias to the interacting edge, wherein a sum of the first bias and the second bias equals the correcting value.

Growing community of inventors

Tainan County, Taiwan

Yu-Shiang Yang