Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Sheng Su

Pin-Chia Su

Tai-Yung Yu

Li-Te Hsu

Ming-Tsao Chiang

Jin-Lin Liang

Kuang-Nian Tang

Yang-Kai Fan

Yu-Cheng Shih

Pin Chia Su

Shu-Huei Suen

Chiang-Jen Peng

Li Te Hsu

Wen-Lang Wu

Hung-Jui Chang

Chia-Cheng Lin

Jin Lin Liang

Shih Cheng Yeh

Jeng-Chang Her

A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.

Semiconductor device structure and method for forming the same

A semiconductor apparatus includes a first tank configured to accommodate a first fluid. A second tank is configured to receive overflow of the first fluid into an upper portion of the second tank and to accommodate a second fluid. A cycling system including a first conduit is configured between the first tank and the second tank. The first conduit has an end substantially below a surface of the second fluid. A fluid providing system including a second conduit is fluidly coupled to the second tank and configured to provide the second fluid into the second tank. The second conduit has an end substantially below the surface of the second fluid. An overflow system is coupled to the second tank and configured to remove an upper portion of the second fluid when the surface of the second fluid is substantially equal to or higher than a pre-determined level.

Wet processing apparatuses

An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate.

Silicon wafer reclamation process

A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.

Method and system for improving wet chemical bath process stability and productivity in semiconductor manufacturing

By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.

A wafer transfer robot for a wafer processing system, such as a wet bench system, and a method for utilizing the robot. The wafer transfer robot can be constructed by a robot arm that is equipped with a plurality of wafer blades each adapted for picking-up and carrying one of a plurality of wafers. The plurality of wafer blades each has a predetermined thickness, a top surface, a bottom surface and a predetermined spacing from adjacent wafer blades. A plurality of sensors, such as optical sensors, capacitance sensors or magnetic sensors, with at least one mounted on the bottom side of one of the plurality of wafer blades for sensing the presence of metal on a wafer carried on an adjacent wafer blade immediately below the one of the plurality of wafer blades.

Wafer transfer robot having wafer blades equipped with sensors

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Tainan, Taiwan

Yu-Sheng Su