Springsoft Usa, Inc.

Yu-Sheng Lu

Hsin-Po Wang

Chia-Ming Chang

Fong-Yuan Chang

Shih-Hsu Huang

Sung-Han Tsai

Ru Lin Yang

Chun-Cheng Chi

Yuan-Kai Ho

Hsueh Liang Hsu

Jia-Zong Lin

Yi-Der Lin

Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.

Methods and systems for reducing clock skew in a gated clock tree

An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified.

System for implementing post-silicon IC design changes

Growing community of inventors

Hsinchu, Taiwan

Yu-Sheng Lu