Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Sheng Chang

Chung-Ju Lee

Tien-I Bao

Cheng-Hsiung Tsai

Yung-Hsu Wu

Ru-Gun Liu

Shau-Lin Shue

Hai-Ching Chen

Tsung-Jung Tsai

Tsai-Sheng Gau

Ming-Feng Shieh

Chia-Tien Wu

Hsiang-Huan Lee

Chun-Kuang Chen

Hsin-Yen Huang

Yung-Sung Yen

A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer. A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

Spacers with rectangular profile and methods of forming the same

A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Lithography using high selectivity spacers for pitch reduction

Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A spacer material layer is formed over the plurality of trenches. A via pattern including a plurality of openings is formed over the spacer material layer and plurality of trenches. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.

Method of forming an interconnect structure for a semiconductor device

A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.

Self-aligned double patterning

A method includes forming a hard mask (HM) stack over a material layer, which has a first, second, third and fourth HM layers. The method also includes forming a first trench in the fourth HM layer, forming a first spacer in the first trench, forming a second trench in the fourth HM layer, removing at least a portion of the first spacer to form a cut by using the third HM layer as an etch-stop layer, removing a portion of the third HM layer and the second HM layer exposed by the first trench, second trench, and cut to form an extended first trench, extended second trench, and extended cut, respectively. The method also includes forming second spacers in the extended first trench, the extended second trench, and the extended cut and removing another portion of the second HM layer to form a third trench.

Method of forming trench cut

Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate. A spacer material layer is formed on a sidewall at least one trench. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.

A method includes forming a patterned hard mask layer, with a trench formed in the patterned hard mask layer, dispensing a Bulk Co-Polymer (BCP) coating in the trench, wherein the BCP coating comprises a mix of a first material and a second material different from the first material. The method further includes treating the BCP coating with a chemical to form a first plurality of strips of the first material and a second plurality of strips of the second material, with the first plurality of strips and the second plurality of strips allocated in an alternating layout. The second plurality of strips is selectively etched, and the first plurality of strips is left in the trench.

Lithography process using directed self assembly

One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled.

Semiconductor patterning

A semiconductor integrated circuit (IC) with a dielectric matrix is disclosed. The dielectric matrix is located between two conductive features. The matrix includes a first nano-scale dielectric block, a second nano-scale dielectric block, and a first nano-air-gap formed by a space between the first nano-scale dielectric block and the second nano-scale dielectric block. The matrix also includes third nano-scale dielectric block and a second nano-air-gap formed by a space between the second nano-scale dielectric block and the third nano-scale dielectric block. The nano-scale dielectric blocks share a first common width, and the nano-air-gaps share a second common width. An interconnect structure integrates the dielectric matrix with the conductive features.

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Taipei, Taiwan

Yu-Sheng Chang