Macronix International Co., Ltd.

Add|on Technology

National Taiwan University

Feeling Technology Corp.

A-power International Co., Ltd.

Auras Technology Ltd.

Yu-Shen Lin

Ray-Lin Wan

Tzeng-Huei Shiau

Chun-Hsiung Hung

Ho-Chun Liou

Hsien-Wen Hsu

Sheree Chou

Lung-Yi Chueh

Han-Sung Chen

Shuo-Nan Hung

Chun Hsiung Hung

Shin-Jang Shen

Wen-Pin Lu

Ray L Wan

Han Sung Chen

Huan-Tsung Chang

Yao-Te Yen

Yuan-Chang Liu

Jin-Lien Lin

Tso-Ming Chang

Yu-Syuan Lin

Lung-Feng Lin

Tzing-Huei Shiau

Chung-Cheng Tsai

Nai-Wen Liu

Ty-Son Ming

Shun-An Hsieh

A detection kit is suitable for detecting a target compound. The detection kit includes a reaction container, an inspection solution composed of a hydrophobic solvent, and a plurality of fluorescent materials. The inspection solution is disposed in the reaction container. The fluorescent materials are dispersed in the inspection solution. The fluorescent material emits fluorescence, and after the fluorescent materials interact with the target compound, the intensity of the fluorescence emitted by the fluorescent materials is reduced.

Detection kit and method for detecting abused drugs

Speaker

An adaptive pulse width control power conversion device includes a pulse width adjustable pulse frequency module (PFM) control circuit, a pulse width modulation (PWM) control circuit, a PWM/PFM switching unit, a switching circuit, and a load status detection circuit. When the power conversion device is to be switched from a PWM mode to a PFM mode, pulse width of a series of PFM control signals is sequentially adjusted from a low value to a high value according to a predetermined pulse width increment until an optimum pulse width is determined and thereafter, an output voltage is supplied to a load in the PFM mode, whereby ripple of output voltage in the PFM mode can be improved and improved stability of output of the power conversion device is realized.

Adaptive pulse width control power conversation method and device thereof

A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.

Voltage-regulating device for charge pump

A nonvolatile memory array is associated with counting memory that stores data on a number of times a particular threshold state is reached in the associated nonvolatile memory. The aging physical characteristics of the nonvolatile memory can be compensated by adjusting the operating conditions of the nonvolatile memory. The operating conditions vary depending on the data stored in the counting memory.

Method and apparatus for changing operating conditions of nonvolatile memory

An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.

Memory array with fast bit line precharge

An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.

Memory array with low power bit line precharge

Low power sense amplifier for amplifying a small current difference associated with a memory cell of a memory array is disclosed. The sense amplifier is connected with a memory array having multiple of even columns and multiple of odd columns. A small read current representing the digital data stored at a memory cell is obtained from the memory array via one of the two complementary data lines. The sense amplifier builds a small voltage difference based on a difference between the small read current and a small reference current obtained from a memory array, and amplifies the small voltage difference to produce two amplified signals. One of the amplified signals is selected by the sense amplifier using an even/odd column decoding scheme. The memory array also uses the even/odd column decoding scheme to output the read current to one of the two complementary data lines. A method for how to use the disclosed sense amplifier is also described.

Low power dissipating sense amplifier

A method for erasing a flash EEPROM. The flash EEROM includes a number of memory units. First, the flash EEPROM is pre-programmed. Second, the step of erasing the flash EEPROM is performed and the flash EEPROM is then soft-programmed. Subsequently, the final step is performed to determine if the erasing step succeeds.

Method for erasing a flash EEPROM

A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.

Voltage-boosting generator for reducing effects due to operating voltage variation and temperature change

A method for making a heat dissipating tube includes the steps of preparing a copper plate, forming a cylindrical tube with a flat bottom and an open end, inserting a copper bar and copper powder into the cylindrical tube, sintering the copper powder to form porous pyrocrystalline copper, removing the copper bar and thus defining a central hole in the porous pyrocrystalline copper, attaching a cap with an drain hole to the open end to close the open end, filling the cylindrical tube with a heat conducting fluid through the drain hole, and drawing a vacuum inside the cylindrical tube through the drain hole and then sealing the drain hole.

Method for making a heat dissipating tube

A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

Method and integrated circuit for bit line soft programming (BLISP)

A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a second node. A first capacitor has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal. A second transistor has a first channel terminal coupled to the second node of the charge pump, and a second channel terminal coupled to its gate and to a third node. A second capacitor has a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal. The first and second transistors comprise a first region and a second region having a first conductivity type providing the first and second channel terminals respectively, a channel region in which the first and second regions are formed having a second conductivity type, and an isolation well having the first conductivity type in a semiconductor substrate. The first and second regions, the channel region and the isolation well form a parasitic bipolar junction transistor that has a threshold voltage. The channel region has a doping concentration establishing a threshold voltage for the MOS transistor which is less than the threshold voltage of the parasitic bipolar junction transistor. The clock signals have sloped rising and falling edges.

Growing community of inventors

Taipei, Taiwan

Yu-Shen Lin