Novatek Microelectronics Corp.

Yu-Shao Liu

Ju-Lin Huang

Chih-Jen Yen

Peng-Yu Chen

Yueh-Hsiu Liu

Hsiu-Hui Yang

Yen-Cheng Cheng

Chin-Hung Hsu

Chun-Yung Cho

Chih-Yung Hsu

Hsin-Yih Li

A layout arrangement of a driver integrated circuit includes multiple output pads, a plurality of switching circuits, and multiple data channel circuits. The output pads include a first output pad and a second output pad and are configurable to be coupled to a plurality of data lines. The switching circuits include a first switching circuit. A first selection terminal of the first switching circuit is coupled to the first output pad via a first connecting wire. A second selection terminal of the first switching circuit is coupled to the second output pad via a second connecting wire. The data channel circuits include a first data channel circuit. An output terminal of the first data channel circuit is coupled to a common terminal of the first switching circuit via a third connecting wire. The third connecting wire is longer than the first connecting wire and the second connecting wire.

Layout arrangement of driver integrated circuit

A driver integrated circuit, including multiple output pads, multiple switching circuits, and multiple data channel circuits, is provided. The output pads and the switching circuits are arranged in a pad area of the driver integrated circuit. The output pads include a first output pad and a second output pad, and the switching circuits include a first switching circuit. A first selection terminal of the first switching circuit is coupled to the first output pad. A second selection terminal of the first switching circuit is coupled to the second output pad. The data channel circuits are arranged in a function circuit area of the driver integrated circuit. The data channel circuits include a first data channel circuit. An output terminal of the first data channel circuit is coupled to a common terminal of the first switching circuit.

Driver integrated circuit

Control methods of a channel setting module applied to a display panel are provided. The display panel has gate lines, source lines, and pixels. The pixels are arranged in matrix. The pixels disposed at the same row are electrically connected to the same gate line, and the pixels disposed at the same column are electrically connected to the same source line. The adoption of the channel setting module reduces the control signals required by the source lines. The channel setting module includes operational amplifiers and de-mux switches, and the control methods dynamically determine conduction states of the de-mux switches. The voltage outputs of the operational amplifiers are selectively outputted to the source lines, depending on conduction statuses of the de-mux switches. By applying the control methods, the interference between the source lines are reduced, and the instantaneous overshoots/undershoots of floating channels are depressed.

Control method of channel setting module applied to display panel

A data driver for driving a display panel includes a first driving channel coupled to a polarity inversion circuit and configured to generate a first data voltage signal having a positive polarity output to the display panel according to a plurality of first pixel data; a second driving channel coupled to the polarity inversion circuit and configured to generate a second data voltage signal having a negative polarity output to the display panel according to a plurality of second pixel data; wherein the first data voltage signal is output to first output node through the polarity inversion circuit during a first line period and the second data voltage signal is output to the first output node through the polarity inversion circuit during a second line period after the first line period, and the first line period and the second line period respectively belong to two consecutive frame periods.

Data driver and driving method for driving display panel

A driving integrated circuit (IC) and a fan-out compensation method thereof are provided. The driving IC includes a plurality of driving channel circuits, a plurality of output buffer circuits and a compensation control circuit. The input terminals of the output buffer circuits are coupled to the output terminals of the driving channel circuits in a one-to-one manner. The output terminals of the output buffer circuits are coupled a plurality of data lines of a display panel in a one-to-one manner. The compensation control circuit is coupled to the output buffer circuits for adjusting the slew rate of the output terminals of the output buffer circuits to compensate difference in delay times between the data lines of the display panel.

Integrated circuit for driving display panel and fan-out compensation method thereof

A gamma-voltage generator is provided to generating a plurality of first gamma voltages and second gamma voltages. At least one of the first gamma voltages generated by DACs of the gamma-voltage generator within a first frame period and at least one of the second gamma voltages generated by the DACs within a second frame period are outputted from a same one of the gamma buffers of the gamma-voltage generator, whereby the transmitted gamma voltages have substantially equal offset. Therefore, the display quality approaches an ideal condition.

Gamma-voltage generator

A frame maintaining circuit including a detection circuit and a display control circuit is provided. The detection circuit detects an unusual status to output a status feedback signal. The display control circuit maintains a frame displayed by a display apparatus according to the status feedback signal until the unusual status ceases.

Frame maintaining circuit and frame maintaining method

An output error compensation method adapted to a multi-input operational amplifier is disclosed. The output error compensation method includes following steps. A plurality of original transconductances of a plurality of differential pairs is obtained regarding a specific combination of input voltages received by the differential pairs. Transconductance differences of a plurality of adjustable differential pairs among the differential pairs are obtained according to the original transconductances. Adjusted transconductance of the adjustable differential pairs are obtained according to the original transconductances and the transconductance differences. Transconductances of the adjustable differential pairs are respectively adjusted according to the adjusted transconductances, so that an output voltage can match an expected value when each of a plurality of combinations of the input voltages is received.

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Kaohsiung, Taiwan

Yu-Shao Liu