Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Shan Lu

Yuan-Ching Peng

Jiun-Ming Kuo

Yu-Bey Wu

Yu-Fan Peng

Wen-Hsing Hsieh

Kuo-Yi Chao

Che-Yuan Hsu

Chung-I Yang

Chih-Han Lin

Shih-Yao Lin

Kuei-Yu Kao

Ming-Yuan Wu

Pei-Yi Liu

Chih-Ching Wang

Chi-Sheng Lai

Wei-Chung Sun

Yen-Po Lin

Li-Ting Chen

Jing Yi Yan

Chen-Yu Chen

Chih-Chung Chang

Wen-Yun Wang

Hung-Ju Chou

Ying-Yan Chen

Yi-Cheng Li

Szu-Ping Lee

Guan-Wei Huang

Chen-Hsuan Liao

Pei-Ling Gao

Hung Yu Lai

Tang Ming Lee

A semiconductor structure includes a fin extending from a substrate and oriented lengthwise in a first direction, where the fin includes a stack of semiconductor layers, an isolation feature disposed over the substrate and oriented lengthwise in a second direction perpendicular to the first direction, where the isolation feature is disposed adjacent to the fin, and a metal gate structure having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers. Furthermore, a sidewall of the bottom portion of the metal gate structure is defined by a sidewall of the isolation feature, and the top portion of the metal gate structure laterally extends over a top surface of the isolation feature.

Multi-gate field-effect transistors and methods of forming the same

A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Dielectric fin structure

A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension Dat a top surface, a second dimension Dat a bottom surface, and a third dimension Dat a location between the top surface and the bottom surface, and wherein each of Dand Dis greater than D.

Semiconductor device structure with uneven gate profile

A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.

Silicon-germanium Fins and methods of processing the same in field-effect transistors

A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

Semiconductor device with varying gate dimensions and methods of forming the same

A method for manufacturing a semiconductor structure includes forming a fin over a substrate, wherein the fin includes first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming an isolation feature around the fin, forming a dielectric feature over the isolation feature, forming a cap layer over the fin and the dielectric feature, oxidizing the cap layer to form an oxidized cap layer, forming source/drain features passing through the cap layer and in the fin, removing the second semiconductor layers in the fin to form nanostructures, and forming a gate structure wrapping around the nanostructures.

Semiconductor structure and method for manufacturing the same

A device comprises a substrate comprising a first portion and a second portion separated by an isolation region, a first gate structure over the first portion, a first drain/source region and a second drain/source region in the first portion and on opposite sides of the first gate structure, wherein the first drain/source region and the second drain/source have concave surfaces, a second gate structure over the second portion and a third drain/source region and a fourth drain/source region in the second portion and on opposite sides of the second gate structure, wherein the third drain/source region and the fourth drain/source have the concave surfaces.

FinFET contact structure and method for forming the same

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Hsinchu County, Taiwan

Yu-Shan Lu