Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Rung Hsu

Chen-Hua Douglas Yu

Chen-Nan Yeh

Cheng-Hung Chang

Chen-Yi Lee

Shih-Ting Hung

Chao-Cheng Chen

Pinyen Lin

Li-Te S Lin

Hsueh-Chang Sung

Liang-Gi Yao

Ming-Huan Tsai

Chu-Yun Fu

Hsien-Hsin Lin

Kuo Bin Huang

Sung Hsun Wu

A semiconductor device and a method of forming the same are disclosed. The method includes forming a fin with a sacrificial layer on a semiconductor substrate, forming isolation regions on the semiconductor substrate and adjacent to the fin, forming a superlattice structure with first and second nanostructured layers on the sacrificial layer, forming a sacrificial structure that surrounds the superlattice structure, forming a first spacer on the superlattice structure, forming an air gap between the superlattice structure and the fin, and forming a second spacer on the fin and below the superlattice structure.

Isolated fin structures in semiconductor devices

A method includes etching a substrate to form a semiconductor fin, forming a gate stack on a top surface and sidewalls of the semiconductor fin, and forming a first recess in the semiconductor fin on a side of the gate stack, wherein forming the first recess comprises, performing a first etching process to form a first portion of the first recess, depositing a first dielectric layer on sidewalls of the gate stack and the first portion of the first recess, performing a second etching process to form a second portion of the first recess using the first dielectric layer as a mask, wherein the second portion of the first recess extends under the gate stack, and performing a third etching process to remove the first dielectric layer.

Semiconductor device and method

A processing apparatus is provided. The processing apparatus includes a chamber and a carrier that is positioned in the chamber for holding a substrate. The processing apparatus further includes a gas inlet connected to the chamber. The gas inlet is configured to supply a process gas into the chamber. The processing apparatus also includes a coil module positioned around the chamber and configured to transfer the process gas into plasma. In addition, the processing apparatus includes a filter disposed in the chamber. The coil module is configured to change a position of the plasma between a first position and a second position, the first position is located between the gas inlet and the filter, and the second position is located between the filter and the carrier.

Processing apparatus and method for forming semiconductor structure

A method for forming a semiconductor device includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process, reshaping the first recess to form a reshaped first recess using a second etching process, wherein the second etching process etches upper portions of the fin adjacent the top of the recess more than the second etching process etches lower portions of the fin adjacent the bottom of the recess, and epitaxially growing a source/drain region in the reshaped first recess. Reshaping the first recess includes performing an oxide etch process, wherein the oxide etch process forms a porous material layer within the recess.

FinFET device and method of forming same

Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.

Semiconductor devices with low junction capacitances and methods of fabrication thereof

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

System and method for source/drain contact processing

Semiconductor devices with low junction capacitances

A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

Reducing resistance in source and drain regions of FinFETs

The present disclosure relates to a structure and method for fin isolation in bulk FinFETs. A sacrificial portion is formed between the actual fin and the substrate, which gets selectively removed at a later stage of processing to reveal a cavity which extends all the way under the fin. This helps prevent source/drain leakage as there is no path for current flow between the fin and bulk substrate. Furthermore, this method of formation helps in precise control of fin-height in bulk FinFETs.

Sacrificial layer fin isolation for fin height and leakage control of bulk finFETs

A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Germanium FinFETs having dielectric punch-through stoppers

A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap.

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Tainan, Taiwan

Yu-Rung Hsu