United Microelectronics Corp.

Yu-Ru Yang

Chien-Hung Chen

Chun-Yuan Wu

Shih-Hsien Huang

Chien-Chung Huang

Huai-Tzu Chiang

Cheng-Tzung Tsai

Chih-Chien Liu

Chao-Ching Hsieh

Sheng-Hao Lin

Hsiao-Pang Chou

Hao-Ming Lee

En-Chiuan Liou

Hui-Lin Wang

Chin-Fu Lin

Chih-Wei Yang

Nien-Ting Ho

Chia-Fu Hsu

Wei Chen

Chun-Yao Yang

Jian-Cun Ke

Yi-Syun Chou

Yu-Feng Liu

Chun-Hsien Lin

Kuo-Chih Lai

Chia-Hsun Tseng

Chia Chang Hsu

Shu Min Huang

Bor-Shyang Liao

Shao-Chung Hu

Min-Chung Cheng

Ssu-I Fu

Yu-Ping Wang

Jiunn-Hsiung Liao

Chi-Mao Hsu

Yuan-Ching Peng

Chien-Ming Lai

Pei-Yu Chou

Yi-Wen Chen

Horng-Bor Lu

Ya-Huei Tsai

Tzung-Yu Hung

Jenn-Tarng Lin

Guang-Yaw Hwang

Tien-I Wu

Lih-Juann Chen

Tsung-Yin Hsieh

Yu-Ting Tseng

Hung-Yi Wu

Yong-Fen Hsieh

Chung Yi Chiu

Kun-Hsin Chen

Chun-Hao Wang

Win-Yi Hsieh

Ju Chun Fan

Po Kai Hsu

Yi Yu Lin

A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Magnetic tunnel junction (MTJ) device and forming method thereof

Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

Resistive random access memory and manufacturing method thereof

A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.

Magnetic tunnel junction structure of magnetic random access memory cell

A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

Semiconductor device and manufacturing method thereof

A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.

Semiconductor structure and manufacturing method thereof

Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

Fin-type field effect transistor and method of forming the same

A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

Manufacturing method of magnetic random access memory cell

The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

Semiconductor structure and the method of making the same

The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.

A resistive random access memory (RRAM) cell includes a substrate, a transistor having a gate on the substrate and a source/drain region in the substrate, a first inter-layer dielectric layer covering the transistor, a contact plug disposed in the first inter-layer dielectric layer and landing on the source/drain region, a resistive material layer conformally covering a protruding upper end portion of the contact plug, and a top electrode on the resistive material layer.

Resistive random access memory (RRAM) and fabrication method thereof

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

Semiconductor device and method for fabricating the same

Growing community of inventors

Hsinchu County, Taiwan

Yu-Ru Yang