Skhynix Inc.

Yu Ri Lim

Jae Il Kim

Min Su Park

Sang Sic Yoon

Hyun Seung Kim

Jin Youp Cha

Sangsic Yoon

A semiconductor device includes a phase difference detection circuit configured to generate a detection signal by detecting a phase difference of a clock and a strobe signal, the detection signal being generated at a logic level of the strobe signal in synchronization with the clock, and configured to generate a write clock by delaying the strobe signal. The semiconductor device also includes a control signal generation circuit configured to store the detection signal, in synchronization with the write clock, and configured to output the stored detection signal as a control signal.

Semiconductor device with phase difference detection circuit between a clock and strobe signal

A semiconductor device includes a data detection circuit configured to detect a number of bits having a predetermined logic level among bits included in data to generate a detection signal. The semiconductor device also includes a selection/transmission circuit configured to output the detection signal or a control data signal as a pre-masking signal based on a selection/transmission signal. The semiconductor device further includes a masking signal generation circuit configured to latch the pre-masking signal based on a pipe input control signal and configured to output the latched signal of the pre-masking signal as a masking signal for controlling a data masking operation based on a pipe output control signal.

Semiconductor devices and semiconductor systems including the semiconductor devices

An error detection circuit may include a selection unit that sequentially selects a primary data group and a secondary data group according to a first control signal and generates an output signal; a first operation unit that performs an error detection operation on the output signal and outputs a preliminary error operation signal; a storage unit that latches the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit that performs an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit and generates an internal error operation signal; and a comparison unit that compares the internal error operation signal with an external error operation signal and outputs a result of the comparison as an error detection signal.

Error detection circuit and semiconductor apparatus using the same

The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.

Semiconductor devices including pipe latch units and system including the same

A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.

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Daejeon, South Korea

Yu Ri Lim