Skhynix Inc.

Yu-Ri Lim

Jung-Hoon Park

Jong-Man Im

Jae-Il Kim

Jin-Hee Cho

A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Semiconductor device

A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.

Memory device and memory system including the same

A semiconductor memory device includes: a plurality of memory areas; a target area setting unit suitable for designating a target area according to a number of accesses to the respective memory areas; a random address generation unit suitable for generating a random address within the respective memory areas in a random manner; a target address generation unit suitable for generating a target address based on the target area and the random address; and a driving unit suitable for performing a smart refresh operation according to the target address.

Semiconductor memory device for performing refresh operation

A memory includes a plurality of word lines, a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines, and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the multiple word lines adjacent to the activated word line when the active duration exceeds a predetermined threshold.

Memory and memory system including the same

A semiconductor device includes a first pad suitable for receiving a first clock that is inputted from an exterior, a second pad suitable for receiving a second clock that is inputted from the exterior, a differential clock recognition unit suitable for recognizing between the first clock and the second clock as a positive clock of differential clocks and recognizing the other as a negative clock of the differential clocks in response to a mirror function signal which represents whether a mirror function is enabled or not, an output unit suitable for outputting an internal signal as an output signal in response to the differential clocks and controlling an output moment of the output signal in response to the mirror function signal and an output moment control signal, and a third pad suitable for supplying the output signal to the exterior.

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Gyeonggi-do, South Korea

Yu-Ri Lim