United Microelectronics Corp.

National Chung Shan Institute of Science and Technology

Tsinghua University

Harvatek Corporation

Yu-Ping Wang

Hui-Lin Wang

Jing-Yin Jhang

Chen-Yi Weng

Hung-Yueh Chen

Chin-Yang Hsieh

I-Ming Tseng

Yi-Hui Lee

Yi-An Shih

Ying-Cheng Liu

Po-Kai Hsu

Ya-Huei Tsai

Hung-Chan Lin

Chien-Ting Lin

Rai-Min Huang

Yi-Wei Tseng

Si-Han Tsai

Che-Wei Chang

Chung-Liang Chu

Yu-Ruei Chen

Jia-Rong Wu

I-Fan Chang

Chien-Ming Lai

Jian-Cheng Chen

Ching-Wen Hung

Wei Chen

Ching-Hua Hsu

Yu-Tsung Lai

Kun-Chen Ho

Yi-Syun Chou

Yu-Ting Tseng

Jun Xie

Chang-Min Li

Chien-Chung Huang

Chun-Tsen Lu

Ching-Hsiang Chiu

Jyh-Shyang Jenq

Yu-Hsiang Lin

Chen-Ming Huang

Kun-Ju Li

Chia-Chang Hsu

Chien-Hao Chen

Hsuan-Hsu Chen

Yu-Chun Chen

Ya-Sheng Feng

Yi-Yu Lin

Ju-Chun Fan

Chiu-Jung Chiu

Yi-Han Ye

Lu-Sheng Chou

Yu-Tung Hsiao

Kun-I Chou

Chin-Cheng Wu

Mon-Sen Lin

Ming-Ta Hsieh

Hao-Yeh Liu

Yi-Rong Zeng

Kuan-You Liu

En-Chiuan Liou

Ssu-I Fu

Tri-Rung Yew

Chi-Mao Hsu

Chih-Wei Yang

Nien-Ting Ho

Heng-Wen Ting

Yu-Ru Yang

Yi-Wen Chen

Chia-Fu Hsu

Chun-Yu Chen

Jian-Cun Ke

Hui-Yen Huang

Tsung-Yin Hsieh

Hung-Yi Wu

Meng-Jun Wang

Hsiu-Hao Hu

Chien-Liang Chang

Jen-Hung Chang

Yu-Feng Liu

Chung-Min Tsai

Chi-Haw Chiang

Ching-Wen Fan

Min-Han Chiu

Ming-Jia Wang

Liang-Huei Jiang

Ren-Ruey Fang

Hsin-I Lu

Yu-Ching Kuo

Yew-Shyang Lay

A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Semiconductor device and method for fabricating the same

An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.

MRAM structure with contact plug protruding out of contact hole and method of fabricating the same

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

A method of manufacturing a magnetoresistive random access memory, including forming a conductive plug in a substrate, forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode material layer on the substrate and the conductive plug, and performing an anisotropic etch process to pattern the bottom electrode material layer, the magnetic tunnel junction material layer and the top electrode material layer, thereby forming a magnetic memory cell on the conductive plug, wherein the anisotropic etch process overetches the conductive plug and the substrate so that a notched portion is formed on one side of an upper edge of the conductive plug, and depressed regions are formed on the substrate at two sides of the magnetic memory cell.

Magnetoresistive random access memory and method of manufacturing the same

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Magnetoresistive random access memory and method for fabricating the same

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Magnetoresistive random access memory

A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Semiconductor structure and method for forming the same

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region

A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer, and patterning the second SOT layer and the passivation layer.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.

A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

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Taoyuan, Taiwan

Yu-Ping Wang