Emc Corporation

Advanced System Products, Inc.

Auspex Systems, Inc.

Yu-Ping Cheng

Santosh C Lolayekar

Renato E Maranon

Wan-Hui Lee

Enyew Tan

Robert Tower Frey

Sanjay Saxena

Anoop R Hegde

Sunil K Asthana

David Hitz

Shih-Tsung Hwang

Ta-Lin Chang

Karl C Chen

A storage switch in accordance with an embodiment of the invention is a highly scalable switch that allows the creation of a SAN that is easy to deploy and that can be centrally managed. Moreover, such a storage switch also allows the deployment of a global infrastructure, allowing the resources of the SAN, such as storage devices, to essentially be positioned anywhere on the globe. Further, such a storage switch allows a multi-protocol SAN, e.g., one that includes both iSCSI or Fibre Channel, and processes data packets at 'wire speed.' To further enable wire-speed processing, a switch in accordance with the invention has 'intelligence' distributed to each of its linecards, through which it classifies packets into data and control packets, it performs virtualization functions, and it performs protocol translation functions. A switch in accordance with the invention further performs serverless storage services such as mirroring, snapshot, and replication.

Virtualization in a storage system

Storage switch for storage area network

Packet classification in a storage system

A system in accordance with an embodiment of the invention provides Quality of Service (QoS) for Storage Access. Such QoS is partially enabled in one embodiment by the automatic pooling of storage devices and provisioning virtual targets from those pools. QoS is enforced in one embodiment by keeping the bandwidth for each connection within a specified range, and particularly, by controlling the number of allowed concurrent requests from an initiator. Load balancing is also provided in one embodiment, improving response times for requests, further easing the ability to provide QoS.

Pooling and provisioning storage resources in a storage network

Enforcing quality of service in a storage network

Protocol translation in a storage system

Switch-based storage services

A host adapter contains a RISC processor, a local memory, and a memory management unit that permits the RISC processor and a host computer system to access a local memory. The host computer system writes command descriptions directly into the local RAM. The RISC processor retrieves and processes the command descriptions. The local RAM may be divided into numbered command description blocks having a fixed size and format. In standard bus protocols, such as SCSI-2, block numbers are used as tag messages. Such tag messages allow the host adapter to quickly identify information used when an SCSI I/O request is resumed. The command description blocks may be linked into lists, including an active list containing command description blocks that are ready for the RISC processor and a free list containing command description blocks that are available for use by the host computer.

System for host accessing local memory by asserting address signal

A data storage system is coupled to a host computer system for the transfer of data between the host and a plurality of data storage devices. The data storage devices are coupled to a plurality of data transfer channels with each data storage channel be coupled to at least a respective one of the data storage devices. Each data transfer channel includes a data buffer and an autonomously operating controller for transferring between the channels data buffer and data storage device. A non-volatile random access storage memory is provided to store cached pages of data. An interface couples the data storage system to the host and through which data is transferred. A reconfigurable data path permits selective data transfer couplings between the data transfers channels, the non-volatile memory, and the interface. A controller directs the configuration of the data path and controls a direct memory access controller for burst transferring data between the interface and the channel data buffers, between the interface and the non-volatile memory and between the non-volatile memory and the channel data buffers.

High-performance non-volatile RAM protected write cache accelerator

A single instance of a device driver is used to control multiple peripheral devices in a computer system having a central processor for executing an operating system, a memory, and first and second interface buses permitting interconnection of peripheral adapters with the central processor. The interface buses each correspond to different classes of peripheral adapters. The device driver includes an initialization routine for scanning the interface buses to identify predetermined functionally related peripheral adapters. A communications path is provided between the operating system and each of the peripheral adapters of a form appropriate for the particular interface bus connected to each adapter. A control path is also provided between each of the peripheral adapters and the operating system of a form appropriate for the particular interface bus connected to each adapter. The device driver provides for the common control and management of the communications and control paths between the operating system and each of the peripheral adapters.

Multiple peripheral adapter device driver architecture

Growing community of inventors

San Jose, CA, United States of America

Yu-Ping Cheng