Nan Ya Technology Corporation

Yu-Pi Lee

Shian-Jyh Lin

Jar-Ming Ho

Ming-Yuan Huang

Shun-Fu Chen

Tse-Chuan Kuo

A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Semiconductor device and fabricating method thereof

A method to determine the predetermined location of a transistor gate of a dynamic random access memory (DRAM). A trench capacitor is respectively provided in a silicon substrate at the two sides of the gate, along the direction of a bit line. The method is to first form a patterned layer of silicon nitride over the substrate so that at the location where the two trench capacitors are desired to be built, the substrate is exposed; then to build the two trench capacitors at the location of the exposed substrate. Form a layer of silicon oxide to cover the capacitors and make the layer of silicon oxide and the layer of silicon nitride at the same level. Layer of silicon nitride is removed afterwards, and a polysilicon layer is conformably formed on the substrate. A BF2 ion implantation is performed twice at different tilt angles on the polysilicon layer in order to define an undoped area between the two trench capacitors. Then remove the undoped area of the polysilicon layer so that part of the silicon substrate is exposed to serve as the predetermined location of transistor gate.

Method to define a transistor gate of a DRAM and the transistor gate using same

A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

Growing community of inventors

Taoyuan County, Taiwan

Yu-Pi Lee