Kabushiki Kaisha Toshiba

Yu Ohata

Koichi Kitahara

Tsuyoshi Kuramoto

Yosuke Takagi

Kazuaki Suzuki

Hirohito Tanabe

Yoshihito Nakayama

Yukiharu Miwa

Masaru Shimbo

A semiconductor device includes a resistor network having a plurality of trimming polysilicon resistors. The polysilicon resistors have the same width and different lengths and can be selectively fused according to the value of current which is caused to flow therein. The resultant resistance of the resistor network is changed by selectively fusing the polysilicon resistors. The output characteristic of the semiconductor device can be adjusted by changing the resultant resistance.

Semiconductor device whose output characteristic can be adjusted by

At least one power output element made of an insulated gate semiconductor element, a surge protection element for an input electrode of the power output element, and a circuit element block for controlling the power output element, are formed on the same semiconductor substrate. A predetermined electrode of the power output element and one end of the surge protection element are connected to each other. In this state, first, second, and third electrode wiring layers are connected to an output terminal of the circuit element block, the other end of the surge protection element, and the input electrode of the power output element, respectively, and the first to third electrode wiring layers are formed separately from one another. In order to connect the first to third electrode wiring layers to each other, a fourth electrode wiring layer is formed thereon. Thus, a characteristic of the power output element is previously evaluated before the fourth electrode wiring layer is formed, using at least the third electrode wiring layer.

Semiconductor device capable of previously evaluating characteristics of

There is a semiconductor device in which an n-type layer formed on a p.sup.+ -type substrate is divided into first and second device forming regions by an isolation region and drive circuit devices and an output circuit device are respectively formed in these first and second device forming regions. The output circuit device is a conductivity modulated MOS transistor having the p.sup.+ -type substrate as a drain and the second device forming regoin as a high resistance region whose conductivity is modulated.

Semiconductor device

A substrate structure for a composite semiconductor device comprises first and second semiconductor substrates whose major surfaces are bonded to each other with an insulating layer interposed therebetween. In this substrate structure, an epitaxial layer is grown from part of the second semiconductor substrate, forming one element area, and another element area is formed in the first semiconductor substrate area and isolated from the epitaxial layer.

Manufacture of a substrate structure for a composite semiconductor

A semiconductor device is provided which has a power insulated-gate MOS field effect transistor and a control semiconductor element formed in a common semiconductor substrate. A first area corresponding to a drain region of low resistance in the power MOS field effect transistor is different in resistivity than a second area corresponding to the control semiconductor element. The electrical characteristics of each element integrated in the devices is substantially equal to the same element in discrete form.

Semiconductor device with isolation between MOSFET and control circuit

In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree. C.

Power MOS FET with carrier lifetime killer

A silicon semiconductor substrate includes an insulating layer embedded therein. The silicon semiconductor substrate comprises a first silicon plate, an insulating layer embedded in the first silicon plate so that the surfaces of the silicon plate and the insulating layer are in a mirror surface, and a second silicon plate united with the first silicon plate and the insulating layer at the mirror surface of the first silicon plate and the insulating layer. The insulating layer is used for forming an isolated region in the second silicon plate.

Silicon semiconductor substrate with an insulating layer embedded

In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree.C.

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Tokyo, Japan

Yu Ohata