Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Yu Nakanishi

Daisuke Iwai

Marie Takada

Naomi Takeda

Kazuhiro Hiwada

Arata Miyamoto

Masanobu Shirakawa

Tokumasa Hara

Hiroshi Yao

Kenichiro Yoshii

Kohei Oikawa

Kiwamu Watanabe

Kenta Yasufuku

Ryo Yamaki

Akira Yamaga

Nobuhiro Kondo

Tetsuya Sunata

Naoaki Kokubun

Hirotsugu Kajihara

Yutaka Ota

Yuji Ishikawa

Ikuo Magaki

Kenji Funaoka

Naoto Oshiyama

Akihiko Fukui

Keigo Hara

According to one embodiment, a memory system includes: a nonvolatile memory including blocks each of which includes physical memory areas; and a memory controller dividing a logical address space into a plurality of banks and associating a block with each of the plurality of banks. The memory controller is configured to: selectively scan a portion related to a first bank among the plurality of banks in a table in which a physical address corresponding to a physical memory area in which valid data is stored is mapped on the logical address space; detect a first physical address corresponding to a first physical memory area in a first block associated with the first bank as a result of the scan; read first valid data stored in the first block based on the first physical address; and write the first valid data in a second block associated with the first bank.

Memory system limiting range of scan in garbage collection

The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks each including a plurality of pages. The controller is configured to sequentially write data from a first page of the plurality of pages when data is written on the plurality of pages. The controller records management information relating to the plurality of blocks in the first page of each of the plurality of blocks.

Memory system and block management method for reducing a load of managing block management information

According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.

Memory device including volatile memory, nonvolatile memory and controller

Memory device including volatile memory, nonvolatile memory and controller receiving refresh command from host

According to one embodiment, an processing system comprises a memory, a receiver, and a transmitter. The memory stores first target information indicating a first target related to a first user, second target information indicating a second target related to a second user, a first rate indicating an achievement rate in a case where the first user has achieved the first target, and a second rate indicating an achievement rate in a case where the second user has achieved the second target. The receiving unit receives first situation information of the first user and second situation information of the second user. The transmitting unit transmits display information obtained by combining a first degree of achievement of the first target derived from the first situation information, a second degree of achievement of the second target derived from the second situation information, the first rate, and the second rate.

Processing system and display device

According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.

Memory system and memory control method

According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command.

Memory system

According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value.

Memory system and constructing method of virtual block

A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.

Storage device

Every time an assignment statement is executed during performing a simulation according to a second variable memory system, it is determined whether a value interpreted to have the same meaning is assigned to the assignment statement in the simulation according to a first variable memory system and in the simulation according to the second variable memory system. When the value interpreted to have the same meaning is not assigned, the value assigned according to the second variable memory system is overwritten by an expected value, and a report indicating that the assignment statement is a part dependent on a variable memory system is output.

Source code analyzing system and source code analyzing method

Growing community of inventors

Yokohama, Japan

Yu Nakanishi