International Business Machines Corporation

Other

Karlsruher Institut Fur Technologie

Massachusetts Institute of Technology

Globalfoundries Inc.

Taiwan Bluestone Technology Ltd.

Bluestone Technologies (cayman) Limited

Yu-Ming Lin

Phaedon Avouris

Damon B Farmer

Jeng-Bang Yau

Yu Zhu

Kuan-Neng Chen

Joerg Appenzeller

Christos Dimitrios Dimitrakopoulos

Keith Aelwyn Jenkins

Michael Engel

Mathias B Steiner

Ralph Krupke

Xin M Zhao

Ali Afzali-Ardakani

Akintunde Ibitayo Akinwande

Mildred S Dresselhaus

Xuesong Li

Oded Rabin

Paul R Herz

Shu-Jen Han

Alfred Grill

Qinghuang Lin

Dirk Pfeiffer

Deborah A Neumayer

Chun-Yung Sung

Alberto Valdes-Garcia

Fengnian Xia

Wenjuan Zhu

Yanqing Wu

Thomas Mueller

A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Solution-assisted carbon nanotube placement with graphene electrodes

A method of forming a transistor comprises forming a conducting substrate layer, forming a dielectric layer over the conducting substrate layer, forming a channel over at least a portion of the dielectric layer and forming first and second source/drain regions contacting respective first and second portions of the channel. The channel comprises a thin-film carbon material. The conducting substrate layer, the dielectric layer, the channel and the first and second source/drain regions are formed such that exposure to radiation causes a change in a threshold voltage of the transistor.

Ultra-sensitive radiation dosimeters

A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer.

Fabrication of graphene nanoelectronic devices on SOI structures

An oscillator circuit includes a field effect transistor and a resonant circuit having a first terminal connected to the field effect transistor. The resonant circuit includes an inductance and a capacitance and has a second terminal for connecting to a radiator. The field effect transistor includes a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The graphene channel is disposed relative to the gate electrode for being biased by the gate electrode into a negative differential resistance region of operation. The oscillator circuit is capable of generating a continuous wave THz frequency signal, and is further capable of being enabled and disabled by the bias applied to the gate electrode.

High frequency oscillator circuit

Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.

Radiation hardened transistors based on graphene and carbon nanotubes

Aspects of the invention are directed to a method for forming a hybrid structure. Initially, a wire is received and an encapsulating film is deposited on the wire. Subsequently, the wire is selectively removed to leave a hollow tube formed of the encapsulating film. A plurality of active particles are then placed into the hollow tube by immersing the hollow tube in a suspension comprising the plurality of active particles and a liquid. Lastly, the hollow tube and the plurality of active particles therein are removed from the suspension and allowed to dry so as to form a cluster of active particles at least partially encapsulated by the encapsulating film.

Graphene hybrid structures for energy storage applications

Aspects of the invention are directed to a method of forming graphene structures. Initially, a cluster of particles is received. The cluster of particles comprises a plurality of particles with each particle in the plurality of particles contacting one or more other particles in the plurality of particles. Subsequently, one or more layers are deposited on the cluster of particles with the one or more layers comprising graphene. The plurality of particles are then etched away without substantially etching the deposited one or more layers. Lastly, the remaining one or more layers are dried. The resultant graphene structures are particularly resistant to the negative effects of aggregation and compaction.

Graphene structures with enhanced stability and composite materials formed therefrom

Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Graphene channel-based devices and methods for fabrication thereof

Aspects of the invention are directed to a method for forming a graphene composite structure. Initially, an encapsulating film is formed on a substrate. The encapsulating film comprises graphene. Subsequently, a plurality of particles are deposited on the encapsulating film, and then a temporary layer is deposited on the plurality of active particles and the encapsulating film. The substrate is then removed. Lastly, the temporary layer is also removed so as to cause the plurality of particles to form a cluster that is at least partially encapsulated by the encapsulating film.

Graphene composite electrodes for energy storage devices

A method includes providing an oscillator having a field effect transistor connected with a resonant circuit. The field effect transistor has a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The method further includes biasing the graphene channel via the gate electrode into a negative differential resistance region of operation to cause the oscillator to generate a frequency signal having a resonant frequency f. There can be an additional step of varying the gate voltage so as to bias the graphene channel into the negative differential resistance region of operation and out of the negative differential resistance region of operation so as to turn on the frequency signal and to turn off the frequency signal, respectively.

High frequency oscillator circuit and method to operate same

Graphene transistor devices and methods of their fabrication are disclosed. In accordance with one method, a resist is deposited to pattern a gate structure area over a graphene channel on a substrate. In addition, gate dielectric material and gate electrode material are deposited over the graphene channel and the resist. Further, the resist and the electrode and dielectric materials that are disposed above the resist are lifted-off to form a gate structure including a gate electrode and a gate dielectric spacer and to expose portions of the graphene channel that are adjacent to the gate structure. Additionally, source and drain electrodes are formed over the exposed portions of the graphene channel.

Graphene transistors with self-aligned gates

Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.

An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.

Growing community of inventors

West Harrison, NY, United States of America

Yu-Ming Lin