Macronix International Co., Ltd.

Yu-Ming Huang

Hsiang-Pang Li

Hsi-Chia Chang

Yung-Chun Li

Chih-Huai Shih

Hsie-Chia Chang

Tei-Wei Kuo

Yuan-Hao Chang

Yu-Ming Chang

Han-Wen Hu

Sheng-Han Wu

Yung-Chun Lee

Kun-Cheng Hsu

Systems, methods, and apparatus including computer-readable mediums for managing error corrections for memory systems are provided. In one aspect, a memory system includes a memory and a memory controller coupled to the memory. The memory controller is configured to: read data from a data page of the memory, perform a first phase Error-Correcting Code (ECC) test on the read data based on first ECC data associated with the data, and in response to determining that the read data fails to pass the first phase ECC test, perform a second phase ECC test on a portion of the read data based on second ECC data. The first ECC data is stored together with the data in the data page. The second ECC data is associated with a portion of the data corresponding to the portion of the read data, and stored in a redundancy page different from the data page.

Managing error corrections for memory systems

A memory chip, a memory device and an operation method are disclosed. The memory chip includes a number of memory units and a control logic circuit. The memory units could be configured as TLC, MLC or SLC. The control logic circuit is configured to use TLC programming approach to program MLC and SLC.

Memory chip, memory device and operation method thereof

Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.

Determining read voltages for memory systems

Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.

Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems with machine learning (ML) are provided. In one aspect, a memory system includes a memory and a memory controller configured to: obtain a first reading output of memory data using a first read voltage corresponding to a first set of parameters associated with the memory data; if the first reading output fails to pass an Error Correction Code (ECC) test, obtain a second reading output of the memory data using a second read voltage corresponding to a second set of parameters associated with the memory data and including the first set of parameters, the second read voltage being generated using at least one ML algorithm based on the second set of parameters; and if the second reading output passes the ECC test, output the second reading output as a target reading output of the memory data.

Determining read voltages for memory systems with machine learning

An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

Encoder, decoder, encoding method and decoding method based on low-density parity-check code

The present disclosure provides a decoding system and method. The decoding system comprises a first decoder and a second decoder. The first decoder is configured to generate an intermediate decoding data by decoding a code data. The second decoder, coupled to the first decoder, wherein the second decoder is configured to generate a plain data by decoding the intermediate decoding data.

Decoding system and decoding method

A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.

Polar code generating method, and electronic device and non-transitory computer-readable storage medium therefor

A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N&#x2212;K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q&#x2212;K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q&#x2212;K frozen bits are allocated to the N&#x2212;K frozen bit-channels and the q additional frozen bit-channels.

Extended polar codes

A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a code word through a polar code transformation. Select a boundary bit-channel among the bit-channels according to a first ranking list for the bit-channels. Identify a target memory cell among the memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation. Decrease a raw bit error rate of the target memory cell.

Control method for memory device and memory controller

An operating method of a memory controller, for a memory device including a plurality of cells, includes steps of: checking states of the cells; marking at least one specific bit-channel according to the states of the cells; and performing an uneven wear leveling scheme on at least one target cell storing messages from the at least one specific bit-channel, such that the wear level of the at least one target cell is different from other cells.

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Taipei, Taiwan

Yu-Ming Huang