Advanced Analog Technology, Inc.

Yu Min Sun

Chu Yu Chu

Mao Chuan Chien

Li Chieh Chen

Chien Chuan Chung

The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor.

Circuit for fixing peak current of an inductor and method thereof

The oscillation circuit includes an output current mirror, a P-N complementary current mirror, a P-type current mirror and an N-type current mirror. The P-N complementary current mirror has the same structure as the output current mirror but has current that is only 1/k times the current of the output current mirror, wherein k is greater than 1. The P-type current mirror connects to the P-N complementary current mirror, and has current that is m times the current of the P-N complementary current mirror, where m is greater than 1. The N-type current mirror has one end connected to the P-type current mirror and another end connected to the output current mirror. The N-type current mirror has current that is n times the current of the P-type current mirror, where and n is greater than 1.

Oscillation circuit having current scaling relationship and the method for using the same

The power transistor circuit with high-voltage endurance includes a first power transistor, a second power transistor and an enabling circuit. The first power transistor includes a first voltage endurance and a first inner resistance, while the second power transistor includes a second voltage endurance and a second inner resistance. The first voltage endurance and the first inner resistance are smaller than the second voltage endurance and the second inner resistance, respectively. The drain of the second power transistor is connected to the drain of the first power transistor and the enabling circuit. The enabling circuit enables the second power transistor first, and when the drain voltage of the first power transistor is smaller than the first endurance, the enabling circuit then enables the first power transistor.

Power transistor circuit and the method thereof

The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The delay circuit is connected to the second-half pulse-generating module. The master-slave register includes a clock, an input end and an output end, wherein the input end is connected to the oscillator-controlling unit, and the clock is connected to the delay circuit.

Circuit for detecting maximal frequency of pulse frequency modulation and method thereof

The low voltage circuit for starting up a synchronous step-up DC/DC converter, which connects to a voltage source through an inductor, includes a P-type power transistor, an N-type power transistor and a controller. The P-type power transistor includes a body diode, and one end of the P-type power transistor acts as a power source of an oscillator. The N-type power transistor connects the P-type power transistor in series, and both of the power transistors are not enabled at the same time. The oscillator electrically connects to the controller, which enables the P-type power transistor at initialization time, and enables the N-type power transistor a period after the initialization time.

Circuit for starting up a synchronous step-up DC/DC converter and the method thereof

The switching method between pulse frequency modulation and pulse width modulation signals is first based on an output voltage of a power transistor to generate a corresponding pulse frequency modulation signal. Next, it is determined whether the corresponding pulse frequency modulation signal has reached its maximal frequency. If so, the initial pulse width modulation signal is adjusted to have the same width as the pulse frequency modulation signal. Thereafter, the adjusted pulse width modulation signal is outputted.

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Hsinchu, Taiwan

Yu Min Sun