United Microelectronics Corp.

Other

National Cheng-kung University

Yu-Min Lin

Chin-Cheng Chien

Tsuo-Wen Lu

Shu-Yen Chan

Jei-Ming Chen

Chun-Wei Hsu

Chia-Lung Chang

Tzung-Ying Lee

Yu-Ren Wang

Chien-Liang Lin

Ying-Wei Yen

Shao-Wei Wang

Wen-Yi Teng

Yi-Ching Wu

Shu-Hui Chen

Chih-Chung Chen

Hung-Hsiang Jen

Yu-Shan Huang

The present invention relates to a method for quantitative measurement of catechol estrogen bound protein in blood sample. By detecting adduction levels of binding sites of the catechol estrogen on the protein in blood sample, the catechol estrogen bound protein in the blood sample can be detected quantitatively and a limit of quantitation can be decreased.

Method for quantitative measurement of catechol estrogen bound protein in blood sample

A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.

Semiconductor device with lower metal layer thickness in PMOS region

A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.

Metal oxide semiconductor transistor and method of manufacturing the same

A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Manufacturing method for metal gate using ion implantation

Growing community of inventors

Tainan, Taiwan

Yu-Min Lin