Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Min Liang

Chi-Yang Yu

Chin-Liang Chen

Kuan-Lin Ho

Jiun-Yi Wu

Jung-Wei Cheng

Wei-Yu Chen

Chien-Hsun Lee

Tsung-Ding Wang

Chung-Shi Liu

Hai-Ming Chen

Chen-Hua Douglas Yu

Hsin-Yu Pan

Wen-Lin Chen

Jiun Yi Wu

Hao-Cheng Hou

Chia-Min Lin

Pei-Rong Ni

Ming-Da Cheng

Chen-Shien Chen

Wei-Hung Lin

Hsiu-Jen Lin

Chien-Chang Lin

Yen-Fu Su

Kai-Chiang Wu

Nien-Fang Wu

A package structure and a manufacturing method thereof are provided. The package structure includes an integrated substrate and a package component. The integrated substrate includes a substrate component laterally covered by an insulating encapsulation, a redistribution structure disposed over the substrate component and the insulating encapsulation, first conductive joints coupling the redistribution structure to the substrate component, and a buffer layer disposed on a lowermost dielectric layer of the redistribution structure and extending downwardly to cover an upper portion of each of the first conductive joints. A lower portion of each of the first conductive joints connected to the upper portion is covered by the insulating encapsulation. The package component disposed over and electrically coupled to the redistribution structure includes a semiconductor die laterally covered by an encapsulant.

Package structure and forming method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.

Semiconductor structure and circuit structure

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.

Package structure and manufacturing method thereof

A semiconductor package provided herein includes a package substrate and a semiconductor device. The package substrate includes a redistribution structure, an interconnect structure bonded to the interconnect structure and an insulation material laterally surrounding the interconnect structure, wherein the redistribution structure has a reduced structure and the insulation material fills the reduced structure. The semiconductor device is bonded to the package substrate. In addition, a method of fabricating a semiconductor package is also provided and includes a precut process forming the reduced structure in the redistribution structure of the package substrate.

Semiconductor package and methods of fabricating a semiconductor package

An electronic component includes a board, an electronic device, and a stiffening structure is provided. The electronic device is disposed on the board. The stiffening structure is disposed on the board. The stiffening structure includes a ring portion corresponding the edge of the board. The stiffening structure includes a core base and a cladding layer. The cladding layer covers the core base.

Electronic component and manufacturing method thereof

A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.

Probe card substrate, substrate structure and method of fabricating the same

A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein. The local interconnect component includes TSVs penetrating through a substrate and electrically coupled to first and second conductive connectors, the first conductive connectors between the first redistribution structure and a first side of the substrate, the second conductive connectors between the second redistribution structure and a second side of the substrate, and a first insulating layer between the first redistribution structure and the first side and laterally covering the first conductive connectors.

Semiconductor structure and forming method thereof

A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Semiconductor package

A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.

Semiconductor packages

A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Semiconductor packages and methods of forming the same

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Semiconductor package and manufacturing method thereof

A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Semiconductor structure and manufacturing method thereof

Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.

Package structure and method of forming the same

A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.

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Taoyuan, Taiwan

Yu-Min Liang