Macronix International Co., Ltd.

Tsinghua University

Yu-Min Hung

Tzung-Ting Han

Cheng-Kuo Sung

Miao-Chih Hsu

Chien-Ying Lee

Chang-Wen Jian

Jia-Wei Lu

Wei-Chih Lee

Hsiang-Lu Wu

Zhang-Hua Fong

A method for manufacturing semiconductor device is provided. A substrate having a memory region and a capacitance region is provided. A plurality of word line structures are formed on the memory region of the substrate. A capacitance structure is formed on the capacitance region of the substrate. The word line structures and the capacitance structure each include a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer, and a second conductive layer on the second dielectric layer. The second conductive layers of the word line structures close to an edge of the memory region and a portion of the second conductive layer of the capacitance structure are removed at the same time to form a trench exposing a portion of the second dielectric layer.

Method for manufacturing semiconductor device

Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.

Self-aligned multiple patterning semiconductor device fabrication

Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of the array and periphery regions in self-aligned quadruple patterning and provide semiconductor devices resulting from the combined patterning.

Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned quadruple patterning

An active/self-sensing compensating hydrostatic bearing is disposed between first and second structures to allow relative movement between the first and second structures. The hydrostatic bearing includes a body and a compensator. The body, fixed to the first structure and separated from the second structure by a first gap, has a chamber and an input passage and an output passage both communicating with the chamber. The compensator is disposed in the chamber. A compensating passage, communicating with the input passage and the output passage, is formed between the body and the compensator. A pressurized fluid flows from the input passage to the output passage through the compensating passage, and the pressurized fluid in the output passage flows to the first gap to maintain the stability and the rigidity for the relative movement between the first and second structures. A hydrostatic bearing module using the hydrostatic bearing is also disclosed.

Active compensating hydrostatic bearing and hydrostatic bearing module using the same

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Taichung, Taiwan

Yu-Min Hung