International Business Machines Corporation

Rohm & Haas Electronic Materials LLC

Front Edge Technology, Inc.

Yu Luo

Bing Dang

Paul Stephen Andry

Adinath S Narasgond

Eric Peter Lewandowski

John Ulrich Knickerbocker

Paul Michael Solomon

Matthew Warren Copel

Christine Armstrong

Hariklia Deligianni

Lubomyr Taras Romankiw

Steven Lorenz Wright

Qiang Huang

Yang Liu

Michael S Gordon

William Joseph Gallagher

Steven Alan Cordes

Sung Kwon Kang

Qianwen Chen

Gregory M Fritz

Michael P Toben

Peter Jerome Sorce

Neil D Brown

Joonah Yoon

Kai Liu

Jae-Woong Nah

Roy Rongqing Yu

Damon B Farmer

Emily R Kinser

Shawn Anthony Hall

Robert L Sandstrom

Janusz Jozef Nowak

Jay A Bunt

Hongqing Zhang

Ryan T Gordon

Elissei Iagodkine

Joana Sofia Branquinho Teresa Maria

David J Lewison

Ying He

Yi Qin

Joyce E Molinelli Acocella

Doreen D DiMilia

Inho Lee

Cristina Camagong

Andrei Fustochenko

Po-wen Cheng

Tung-hsiu Shih

Mengnian Niu

Kai-wei Nieh

Masaaki Imanari

Devices, systems, and/or methods that can facilitate plating one or more metal layers onto a niobium-titanium substrate are provided. According to an embodiment, a device can comprise a niobium-titanium substrate. The device can further comprise a first metal layer plated on a portion of the niobium-titanium substrate. The device can further comprise a second metal layer plated on the first metal layer. The device can further comprise a third metal layer plated on the second metal layer.

Electroplated metal layer on a niobium-titanium substrate

Aspects of the invention include a non-destructive bond line thickness measurement of thermal interface material on silicon packages. A non-limiting example computer-implemented method includes receiving a chip mounted on a laminate and depositing a high-density material on the chip. The computer-implemented method deposits a thermal interface material on the chip and lids the chip, and the laminate with a lid. The computer-implemented method X-rays the lid, the chip, and the laminate to produce an X-ray and measures, using a processor, from the X-ray a bond line thickness of the TIM as a distance from a bottom of the lid to a top surface of the high-density material.

Non-destructive bond line thickness measurement of thermal interface material on silicon packages

A method for forming a nanostructure includes coating an exposed surface of a base layer with a patterning layer. The method further includes forming a pattern in the patterning layer including nano-patterned non-random openings, such that a bottom portion of the non-random openings provides direct access to the exposed surface of the base layer. The method also includes depositing a material in the non-random openings in the patterning layer, such that the material contacts the exposed surface to produce repeating individually articulated nano-scale features. The method includes removing remaining portions of the patterning layer. The method further includes forming an encapsulation layer on exposed surfaces of the repeating individually articulated nanoscale features and the exposed surface of the base layer.

Nanostructure featuring nano-topography with optimized electrical and biochemical properties

Present disclosure relates to magnetic materials, chips having magnetic materials, and methods of forming magnetic materials. In certain embodiments, magnetic materials may include a seed layer, and a cobalt-based alloy formed on seed layer. The seed layer may include copper, cobalt, nickel, platinum, palladium, ruthenium, iron, nickel alloy, cobalt-iron-boron alloy, nickel-iron alloy, and any combination of these materials. In certain embodiments, the chip may include one or more on-chip magnetic structures. Each on-chip magnetic structure may include a seed layer, and a cobalt-based alloy formed on seed layer. In certain embodiments, method may include: placing a seed layer in an aqueous electroless plating bath to form a cobalt-based alloy on seed layer. In certain embodiments, the aqueous electroless plating bath may include sodium tetraborate, an alkali metal tartrate, ammonium sulfate, cobalt sulfate, ferric ammonium sulfate and sodium borohydride and has a pH between about 9 to about 13.

Electrolessly formed high resistivity magnetic materials

A subtractive forming method that includes providing a material stack including a samarium and selenium containing layer and an aluminum containing layer in direct contact with the samarium and selenium containing layer. The samarium component of the samarium and selenium containing layer of the exposed portion of the material stack is etched with an etch chemistry comprising citric acid and hydrogen peroxide that is selective to the aluminum containing layer. The hydrogen peroxide reacts with the aluminum containing layer to provide an oxide etch protectant surface on the aluminum containing layer, and the citric acid etches samarium selectively to the oxide etch protectant surface. Thereafter, a remaining selenium component of is removed by elevating a temperature of the selenium component.

Wet etching of samarium selenium for piezoelectric processing

Vertical via connections to a battery are hermetically sealed to prevent environmental factors (e.g. moisture, oxygen, and nitrogen) from entering the internals of the battery through porous conductive material filling the vias resulting in reduced battery performance and battery failure.

Hermetial via seal for thin film battery

A subtractive forming method for piezoresistive material stacks includes applying an etch chemistry to an exposed first portion of a piezoresistive material stack. The etch chemistry includes a citric acid component for removing a first element of a piezoelectric layer of the piezoresistive material stack selectively to a surface oxide. At least one second element of the piezoelectric layer remains. The method further includes heating the piezoresistive material stack after said applying the etch chemistry to vaporize the at least one second element. A second portion of the piezoresistive material stack is protected from the removal and the heating by a mask.

A battery comprising an anode comprising anode material in contact with a metal anode current collector. The battery further comprises a cathode comprising cathode material in contact with a cathode current collector comprising a transparent conducting oxide (TCO). The battery further comprises an electrolyte with a pH in a range of 3 to 7.

Cathode for thin film microbattery

A method of providing an anode composed of a homogeneous solid metallic alloy is provided. The alloy includes 100 ppm to 1000 ppm Bi, 100 ppm to 1000 ppm In, and Zn. The method includes fabricating a cathode in a first cavity in a first dielectric element. The method further includes fabricating an anode in a second cavity in a second dielectric element. The method further includes joining the cathode and the anode in a complanate manner.

Method of forming a homogeneous solid metallic anode for a thin film microbattery

A method of electrolessly plating an iron-based substrate, including immersing an iron-based substrate in an acidic solution, immersing the iron-based substrate in a basic complexing solution, immersing the iron-based substrate in a catalytic metal solution including a catalytic metal, and immersing the iron-based substrate in an electroless nickel plating solution or an electroless cobalt plating solution.

Pretreatment of iron-based substrates for electroless plating

A method provides a structure that includes a substrate having a metal layer disposed on a surface and a metal feature disposed on the metal layer. The method further includes immersing the structure in a plating bath contained in an electroplating cell, the plating bath containing a selected solder material; applying a voltage potential to the structure, where the structure functions as a working electrode in combination with a reference electrode and a counter electrode that are also immersed in the plating bath; and maintaining the voltage potential at a predetermined value to deposit the selected solder material selectively only on the metal feature and not on the metal layer. An apparatus configured to practice the method is also disclosed.

Selective solder plating

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 &#x3bc;m). The subarray probe tips may be on a pitch at or less than fifty microns (50 &#x3bc;m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

Test probe head for full wafer testing

Embodiments include methods and products for evaluating microbatteries. The microbattery includes a cathode layer, an anode layer physically separated from the cathode layer, and an electrolyte layer in contact with the anode and the cathode. The microbattery also includes at least one auxiliary electrode in physical contact with the electrolyte layer, the auxiliary electrode containing at least one metal coating and at least one non-conductive film, wherein the at least one metal coating is physically separated from the cathode and the anode.

Micro battery design and diagnosis

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Hopewell Junction, NY, United States of America

Yu Luo