Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Lung Yeh

Ming-Chi Wu

Chien-Chang Huang

Chien-Nan Tu

Chi-Yuan Wen

Chien Nan Tu

Shih-Shiung Chen

Chun-Chieh Fang

Hsing-Chih Lin

Yen-Hsiu Chen

Yung-Hsiang Chen

Kun-Yu Lin

Wei-Liang Chen

Ji-Heng Jiang

Po-Han Huang

Ji Heng Jiang

Hsin-Yi Kuo

Chuang Chihchous

Ting-Ying Wu

Jiech-Fun Lu

Ming-Hsien Wu

Kuan-Chi Tsai

Ching-Chung Su

Jian Yuan Wu

Ching-Hung Huang

Bo-Chang Su

Wei-Tung Huang

Che-Hsiang Hsueh

Li-Ming Sun

Cheng-Hsien Chen

Yeur-Luen Tu

Cheng-Ta Wu

Yu-Hung Cheng

Ru-Liang Lee

Victor Y Lu

Chih-Hsun Lin

Pu-Fang Chen

Chieh-Shuo Liang

Po-Jung Chiang

Shi-Chieh Lin

Yi-Ping Pan

Yen-Hsiang Hsu

Hung-San Lu

Ying-Tsang Ho

Kun-Mao Wu

Li Chun Liu

Chu-We Hu

Chihchous Chuang

Tsai-Ji Liou

Ching Feng Lee

Chih Hung Wang

Chun Tang Wang

Li-Te Hsu

Wei-Kung Tsai

Kuo-Yu Cheng

Yong-En Syu

Jian Wu

Chih-Ho Tai

Pin-Chia Su

Keng-Yu Chen

Shao-Yu Chen

Meng-Yi Wu

Chu-Sheng Lee

Shuo Yen Tai

Kai-Lan Chang

Jung-Yu Cheng

Shih-Chang Lin

Sheng-Hung Chou

A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.

Passivation layer for a semiconductor device and method for manufacturing the same

A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Deep trench isolation structures resistant to cracking

An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

LDMOS device having isolation regions comprising DTI regions extending from a bottom of STI region

A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

Method and system for forming metal-insulator-metal capacitors

A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

Surface damage control in diodes

A method is provided that includes forming a first metal layer of a seal structure over a micro-electromechanical system (MEMS) structure and over a channel formed through the MEMS structure to an integrated circuit of a semiconductor structure. The first metal layer is formed at a first temperature. The method includes forming a second metal layer over the first metal layer. The second metal layer is formed at a second temperature less than the first temperature. The method includes performing a first cooling process to cool the semiconductor structure.

Semiconductor structure and formation thereof

A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.

Plating membrane

A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Semiconductor arrangement comprising isolation structure comprising at least two electrical insulator layers

A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.

Semiconductor device including deep trench isolation structure comprising dielectric structure and copper structure and method of making the same

Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Fabrication method of metal-free SOI wafer

A semiconductor device includes a device layer, a semiconductor layer, a sensor element, a dielectric layer, a color filter layer, and a micro-lens. The semiconductor layer is over the device layer. The semiconductor layer has a plurality of microstructures thereon. Each of the microstructures has a substantially triangular cross-section. The sensor element is under the microstructures of the semiconductor layer and is configured to sense incident light. The dielectric layer is over the microstructures of the semiconductor layer. The color filter layer is over the dielectric layer. The micro-lens is over the color filter layer.

CMOS image sensor structure with microstructures on backside surface of semiconductor layer

An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Image sensor device with reflective structure

An image sensor with high quantum efficiency is provided. In some embodiments, a semiconductor substrate includes a non-porous semiconductor layer along a front side of the semiconductor substrate. A periodic structure is along a back side of the semiconductor substrate. A high absorption layer lines the periodic structure on the back side of the semiconductor substrate. The high absorption layer is a semiconductor material with an energy bandgap less than that of the non-porous semiconductor layer. A photodetector is in the semiconductor substrate and the high absorption layer. A method for manufacturing the image sensor is also provided.

Image sensor with a high absorption layer

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Kaohsiung, Taiwan

Yu-Lung Yeh