Nxp B.v.

Yu Lin

Vladislav Dyachenko

Erwin Janssen

Konstantinos Doris

Marcello Ganzerli

Athon Zanikopoulos

Frank Leong

Maarten Lont

Mingda Huang

Chuang Lu

A radar unit () for detecting an existence of interference is described that includes: a millimetre wave (mmW) transceiver (Tx/Rx) circuit configured to radiate a transmit radar signal and receive an echo signal thereof; a mixed analog and baseband circuit operably coupled to the mmW Tx/Rx circuit; and a signal processor circuit () operably coupled to the mixed analog and baseband circuit. An interference detection unit () is operably coupled to the mmW Tx/Rx circuit and configured to: monitor a whole or a portion of a radar frequency band supported by the radar unit and identify, from a received interference signal, an arrival direction of the identified interference and a level of interference and output an interference detected signal; and wherein the signal processor circuit () is configured to analyse the interference detected signal and quantify a response to the detection of an arrival direction and a level of received interference.

Radar unit, integrated circuit and methods for detecting and mitigating mutual interference

A communication unit, such as a radar unit () includes a plurality of cascaded millimetre wave, mmW, transceiver, TRx, circuit, each comprising at least one phase shift circuit () and each coupled to respective antennas; and a signal processor circuit () operably coupled to the plurality of cascaded mmW TRx circuits and configured to process transmit and receive signals of the plurality of cascaded mmW TRx circuits. The radar unit () further comprises: a first TRx circuit () of the plurality of cascaded mmW TRx circuits being configured to wirelessly transmit () a signal to a second TRx circuit () via a respective antenna; a localization processing circuit () operably coupled to at least one of the first TRx circuit () and second TRx circuit () and configured to wirelessly determine a distance relationship () between at least one antenna coupled to the first TRx circuit () and at least one antenna coupled to the second TRx circuit (); and a phase control unit (), operably coupled to the localization processing circuit () and configured to adjust at least one phase shifter () in response to the wirelessly determined distance relationship.

Communication unit, integrated circuits and methods for cascading integrated circuits

A successive approximation register, SAR, analog-to-digital converter, ADC, () is described. The SAR ADC () includes: a track and hold circuit () configured to sample an analog input signal (); a comparator () coupled to the track and hold circuit and configured to compare the sampled analog input signal () with a DAC () output voltage; and a feedback path () that comprises a digital-to-analog converter, DAC, () configured to generate the reference voltage that approximates the input analog signal (). The SAR ADC () further includes a dither circuit () coupled to or located in the feedback path () and arranged to add a dither signal at an input of the DAC () in a first time period and subtract the dither signal from the output digital signal routed via the feedback path () and input of the DAC () in a second time period during a conversion phase of the SAR ADC ().

Successive approximation register (SAR) analog-to-digital converter (ADC), radar unit and method for improving harmonic distortion performance

A radar unit () for detecting an existence of interference is described that includes: a millimetre wave (mmW) transceiver (Tx/Rx) circuit configured support a normal data acquisition mode of operation that comprises transmitting a radar signal waveform and receiving an echo signal thereof; a mixed analog and baseband circuit operably coupled to the mmW Tx/Rx circuit; and a signal processor circuit () operably coupled to the mixed analog and baseband circuit. An interference detection unit () is operably coupled to the mmW Tx/Rx circuit. The radar unit is configured to operate a time-discontinuous mode of operation that includes a first time portion used as an interference monitoring period and a second time portion used by the radar unit in the normal data acquisition mode of operation, whereby the mixed analog and baseband circuit, signal processor circuit () and interference detection unit () are configured to detect interference signals during the monitoring period.

A reconfigurable radar unit is described that includes: a millimetre wave (mmW) transceiver (Tx/Rx) circuit; a mixed analog and baseband integrated circuit; and a signal processor circuit. The mmW Tx/Rx circuit and mixed analog and baseband integrated circuit and signal processor circuit are configured to support a plurality of radar operational modes. a radar sensitivity monitor and architecture reconfiguration control unit () is coupled to the signal processor circuit and is configured to monitor a radar performance and, in response thereto, initiate a change in the radar operational mode. In this manner, a large number of radar operational modes is supported and can be dynamically adopted by the reconfigurable radar unit dependent upon any prevailing radar performance condition.

Reconfigurable radar unit, integrated circuit and method therefor

An analog-to-digital converter (ADC) and a method are disclosed. The ADC includes dithering circuitry. The dithering circuitry includes a signal level detector, a dither amplitude controller, a random code generator, and a dither digital-to-analog converter (DAC). The signal level detector receives the analog input signal and provides amplitude level information associated with the analog input signal. The dither amplitude controller receives the amplitude level information from the signal level detector, and provides a control signal. The dither amplitude controller varies the control signal based on the amplitude level information. The dither DAC receives the control signal from the dither amplitude controller and a pseudo-noise (PN) signal from the random code generator, and provides the dither signal based on the control signal. The dither signal varies based on an amplitude level of the analog input signal.

Signal amplitude aware dithering method for enhancing small signal linearity in an analog-to-digital converter

A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component.

Method and apparatus for generating a frequency estimation signal

A receive path arrangement of a radar sensor of FMCW type comprising a first and second receive path configured to receive reflected radar signals for detection and ranging of objects in a space around the radar sensor;

Receiver path arrangement

A successive approximation register, SAR, analog-to-digital converter, ADC, () is described. The SAR ADC () includes: an analog input signal (); an ADC core () configured to receive the analog input signal () and comprising: a digital to analog converter, DAC () located in a feedback path; and a SAR controller () configured to control an operation of the DAC (), wherein the DAC () comprises a number of DAC cells, arranged to convert a digital code from the SAR controller () to an analog form; a digital signal reconstruction circuit () configured to convert the digital codes from the SAR controller () to a binary form; and an output coupled to the digital signal reconstruction circuit () and configured to provide a digital data output (). The DAC () is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller () is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC () and the digital signal reconstruction circuit () to implement a small signal mapping mode of operation.

Successive approximation register analog-to-digital converter, electronic device and method therefor

The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

Reconfigurable Ethernet receiver and an analog front-end circuit thereof

Methods and systems for performing analog-to-digital conversion are described. In one embodiment, a method for performing analog-to-digital conversion involves processing an analog impulse signal to obtain an impulse pattern of the analog impulse signal in a first signal processing path and converting the analog impulse signal into a digital signal based on the impulse pattern in a second signal processing path that is in parallel with the first signal processing path. The impulse pattern of the analog impulse signal includes duty cycle information of the analog impulse signal. Other embodiments are also described.

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Utrecht, Netherlands

Yu Lin