Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Lite-on It Corporation

Harvatek Corporation

Econet (suzhou) Limited

Yu-Lin Chu

Hsi-Yu Kuo

Chin-Yuan Ko

Chih-Wei Hsu

Tsung-Yuan Chen

Feng-Chih Chang

Ko-Yi Lee

Hsin-Hsien Li

Lu-Kang Mao

Shih-Jen Li

Li-Yu Chiu

Bing-Hsun Lu

Chung-Ching Huang

Chih-Chia Cheng

In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.

Electrostatic discharge protection for integrated circuit during back end-of-line processing

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well and doped regions. The substrate has heavily doped and lightly doped regions over the heavily doped region. The first wells are disposed in the lightly doped region and arranged as an array. The first wells have a conductive type opposite to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region, and has an active region defined by an isolation structure. The first wells are overlapped with the second well. Top ends of the first wells are lower than a bottom end of the second well. The doped regions are separately located in the active region, and have a conductive type opposite to a conductive type of the second well.

Semiconductor device with improved electrostatic discharge or electro-over stress protection

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, and first and second doped regions. The substrate has heavily doped and lightly doped regions. The lightly doped region is disposed over the heavily doped region. The first well is disposed in the lightly doped region. The first well has a conductive type complementary to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region. A location of the first well overlaps a location of the second well. The first and the second doped regions are located in the second well within the active region, and spaced apart from each other. The first and the second doped regions have a same conductive type complementary to a conductive type of the second well.

Semiconductor device comprising deep counter well and manufacturing mehtod thereof

An IC structure includes a substrate, a deep n-well (DNW), a first device, a second device, a first electrical path and a second electrical path. The DNW is in the substrate. The first device is formed inside the DNW and connected to a first lower reference voltage and a first higher reference voltage. The second device is formed in the substrate and outside the DNW, and connected to a second lower reference voltage and a second higher reference voltage. The first electrical path is electrically connected between the first device and the second device. The second electrical path is electrically connected between the first lower reference voltage and the second lower reference voltage. A second metal layer that includes the second electrical path is located in an area outside of an area above a first metal layer in which the first electrical path is located.

Integrated circuit structure

A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip.

Package structures

An IC structure is provided. The IC structure includes a P-type substrate, a deep N-well region in the substrate, a first N-well region on the deep N-well region, a first N-type doped region in the first N-well region, a second N-well region in the substrate, a first P-well region in the substrate, and a discharge circuit. The second N-well region and the first P-well region are separated from the deep N-well region. The discharge circuit includes a first P-type doped region in the first P-well region, a first PMOS transistor formed in the second N-well region, a first electrical path coupled between a source of the first PMOS transistor and the first N-type doped region, and a second electrical path coupled between a drain of the first PMOS transistor and the first P-type doped region.

IC structure

An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a second power line. The first circuit is in the DWN. The second circuit is outside the DWN and electrically connected with the first circuit. The first power line is configured to provide the first circuit with power. The second power line is configured to provide the second circuit with power. The second power line is electrically connected with the first power line. The first power line and the second power line are in different conductive layers.

Semiconductor device and method of manufacturing the same

An electronic device is disclosed that includes an output device and a detection circuit. The output device is coupled to an output pad, and is turned on according to a protection signal. The detection circuit is configured to detect a voltage level of a control node, to generate the protection signal based on the detected voltage level, and to switch the voltage level to a predetermined voltage level according to the detected voltage level.

Protection circuit for output device

The semiconductor device for fabricating an IC is provided. The semiconductor device includes a deep n-well (DNW), a first inverter, a second inverter, an electrical path, and a charge-dispelling device. The DNW is formed in a substrate. The first inverter is formed inside the DNW. The second inverter is formed in the substrate and outside the DNW. The electrical path is arranged between the first inverter and the second inverter. The charge-dispelling device is connected between the ground of the first inverter and the ground of the second inverter to develop a bypass path. The impedance of the bypass path is lower than the impedance of the electrical path.

Semiconductor device to dispel charges and method forming the same

A circuit that includes a first diode-connected dummy device, a second diode-connected dummy device, a third diode-connected dummy device, a fourth diode-connected dummy device, and a first discharge path. The second diode-connected dummy device connected in cascode with the first diode-connected dummy device. The fourth diode-connected dummy device connected in cascode with the third diode-connected dummy device. The first and the second diode-connected dummy devices are formed in a first region. The third and the fourth diode-connected dummy devices are formed in a second region which is outside the first region. The first discharge path configured to discharge charges from at least one of the first and the second diode-connected dummy devices in the first region to a reference voltage terminal of one of the third and the fourth diode-connected dummy devices in the second region.

Protection circuit

The present invention provides a compound of formula I wherein A, B and C are a repeating unit; each of A and B is an optionally substituted group for forming a conjugated polymer; C is a crosslinkable group; and n is an integer equal to or greater than 1. The present invention further provides an element and an electronic device using the compound of formula I, and more particularly, provides a light emitting diode (LED) device using the compound of formula I.

Compound for carrier transport, element and electronic device using the same

A parallel hybrid circuit comprising a transformer, a first matching resistor, a second matching resistor and an echo cancelling circuit. The transformer comprises: a first side, comprising a transmitting coil group and a receiving coil group, wherein the transmitting coil group comprises at least one transmitting coil, wherein the receiving coil group comprises at least one receiving coil; a second side comprising at least one transceiving coil; wherein the transformer receives a transmitting signal and couples the transmitting signal from the first side to the second side via a first turn ratio, and receives a receiving signal from the transceiving line and couples the receiving signal from the second side to the first side via a second turn ratio. The first, second matching resistors are coupled with the transformer in parallel. The echo cancelling circuit is coupled between the transmitting line and the receiving line.

Parallel hybrid circuit

A generating system includes a first generating device () and a second generating device (). The first generating device includes a housing (), a solar cell panel (), a storage unit (), a heat conduction layer (), a heating chamber () and a plurality of water pipes (). The second generating device includes an impeller (), a propeller shaft () and a generator (). Thus, the first generating device can receive the solar energy to produce an electric power, and the second generating device is driven by the wind power and the water power to generate an electrical energy so that the generating system can use the natural resources to produce an electrical energy at the day and the night so as to enhance the generating efficiency of the generating system.

Generating system using solar energy and wind power

A lamp includes a housing unit and a light source mounted on the housing unit. The housing unit includes a housing and a plurality of heat radiating fins. The light source includes a support base having a first side provided with a plurality of light emitting members, a heat radiating assembly having a first end mounted on a second side of the support base and a heat conducting plate mounted on a second end of the heat radiating assembly.

Growing community of inventors

Hsinchu, Taiwan

Yu-Lin Chu