Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Lien Huang

Tung Ying Lee

Ching-Feng Fu

Chi-Wen Liu

Guan-Ren Wang

Ming-Huan Tsai

Chun-Hsiang Fan

Clement Hsingjen Wann

Huan-Just Lin

Chun Hsiung Tsai

Chi-Kang Liu

Yung-Ta Li

De-Wei Yu

Zhao-Cheng Chen

Yun-Min Chang

Li-Te S Lin

Meng-Chun Chang

Chii-Ming M Wu

Tsai-Jung Ho

Chung-Hsien Chen

Che-Ming Hsu

Winnie Chen

Ziwei Fang

Tung-Ying Lee

Tsu-Hsiu Perng

Peng Wang

Bor Chiuan Hsieh

Yi-Chen Lo

Tsai-Chun Li

Cheng-Hua Yang

Hun-Jan Tao

Neng-Kuo Chen

Da-Wen Lin

Han-Yu Lin

Huang-Ming Chen

Meng-Ku Chen

Guan-Xuan Chen

Yang-Cheng Wu

Kun-Yen Lu

Fu-Sheng Li

Tze-Liang Lee

Ling-Yen Yeh

Chia-Pin Lin

Jr-Hung Li

Xiong-Fei Yu

Sheng-Hsiung Wang

Yuan-Hung Chiu

Chun-Fu Cheng

You-Ru Lin

Fan-Yi Hsu

Sheng-Wen Yu

Chun-Liang Tai

Pei-Yi Lin

Jim Cy Huang

Chi-Hao Chang

Chun-Hsiung Lin

Weng Chang

Chun-Wei Chang

Tsz-Mei Kwok

Shiang-Bau Wang

Tsan-Chun Wang

Hsiang-Ku Shen

Sey-Ping Sun

Chien-Tai Chan

Cheng-Hung Chang

Jeng-Ya David Yeh

Zhen-Cheng Wu

I-Ming Chang

Wen-Sheh Huang

Hao-Ming Lien

Yi-An Lin

Han-Pin Chung

Yi-Chen Huang

Chin-Chi Wang

Yi-Shan Chen

Tsung-Hung Lee

Shwang-Ming Cheng

Janet Chen

Mao-Rong Yeh

Kuan-Da Huang

Chuan-Hui Lu

Wilson Huang

D T Lee

Kai-Ting Tseng

Various semiconductor techniques described herein enable reductions in one or more sizes of a fin field-effect transistor (finFET) and/or increasing one or more sizes of a finFET. In various implementations described herein, a material may be used to reduce the one or more x-direction sizes of the finFET by selective deposition while enabling the one or more y-direction sizes of the finFET to be increased or enlarged by etching. The x-direction size of a source or drain of the finFET, the x-direction size of an active region of the finFET, and/or the x-direction size of a polysilicon region of the finFET may be increased by selective deposition of a boron nitride (BN), a boron carbide (BC), a boron oxide (BO) (e.g., boric oxide (BO), a fluorocarbon (CxFy) polymer, and/or another material.

Semiconductor devices and methods of manufacture

A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.

Semiconductor device and method

Embodiments of the present disclosure relates to a semiconductor device structure, including a first gate dielectric layer having a top surface and a corner surface, wherein a highest point of the top surface of the first gate dielectric layer is at a first elevation. The semiconductor device structure includes a first gate electrode layer having a top surface, wherein a highest point of the top surface of the first gate electrode layer is at a second elevation higher than the first elevation. The semiconductor device structure includes a first dielectric cap layer in contact with the top surface and the corner surface of the first gate dielectric layer. The first dielectric cap layer is also in contact with the top surface of the first gate electrode layer. The semiconductor device structure includes a first gate spacer in contact with the first dielectric cap layer and the first gate dielectric layer.

Semiconductor device structure and methods of forming the same

In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Semiconductor devices

The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length.

Conductive feature formation

A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.

Self aligned contact scheme

In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Semiconductor device isolation features

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Fin field-effect transistor device having contact plugs with re-entrant profile

A method for fabricating a semiconductor device comprises forming a gate electrode structure over a first region of a semiconductor substrate, and forming a source/drain region on a second region of the semiconductor substrate. The gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and gate sidewalls. The second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer. The method for fabricating a semiconductor device further comprises forming an interlayer dielectric layer over the source/drain regions and the gate sidewall, and forming an oxide layer over the source/drain region and the gate sidewall without substantially forming the second oxide layer on the gate electrode layer.

Method of fabricating a semiconductor device

A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.

Asymmetric source/drain epitaxy

A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Gap patterning for metal-to-source/drain plugs in a semiconductor device

Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming fins from a substrate, forming a gate stack over portions of the fins, forming an epitaxial source/drain region adjacent the gate stack, depositing a dielectric layer over the epitaxial source/drain region, forming an opening in the dielectric layer, and forming a gapfill in the opening in a bottom-up fashion. The gapfill includes Si or W. The method further includes forming a conductive feature over the epitaxial source/drain region and replacing the gapfill with a dielectric material.

Methods of forming semiconductor device structures

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Middle-of-line interconnect structure and manufacturing method

A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

Gate structures in transistor devices and methods of forming same

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Jhubei, Taiwan

Yu-Lien Huang